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    Multi-engine address translation facility
    1.
    发明授权
    Multi-engine address translation facility 有权

    公开(公告)号：US10956341B2

    公开(公告)日：2021-03-23

    申请号：US16752754

    申请日：2020-01-27

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Uwe Brandt ,  Markus Helms ,  Christian Jacobi ,  Markus Kaltenbach ,  Thomas Koehler ,  Frank Lehnert

    IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/455

    Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

    MULTIPROCESSOR COMPUTER SYSTEM
    4.
    发明申请
    MULTIPROCESSOR COMPUTER SYSTEM 有权
    多处理器计算机系统

    公开(公告)号：US20160048453A1

    公开(公告)日：2016-02-18

    申请号：US14813603

    申请日：2015-07-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Thomas Koehler ,  Frank Lehnert

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/681

    Abstract: A computer system has physical processors supporting virtual addressing. Virtual processors represent multiple execution threads, and logical state of all threads of a virtual processor is stored in a state descriptor field in main memory when the virtual processor is removed from one of the physical processors. Each thread has assigned a thread identifier, which is unique in the respective virtual processor only, and each virtual processor has assigned a unique state descriptor identifier. Address translations for the threads of the multiple virtual processors under their respective thread identifier and state descriptor identifier are stored, and a sequence number is generated when an entry in the translation lookaside buffer is created. The sequence number is stored together with a respective thread identifier, state descriptor identifier, and a valid bit in a respective translation lookaside buffer entry. A determination is made as to whether an address translation is stored in the translation lookaside buffer for a current thread identifier and a current state descriptor identifier by comparing the translation lookaside buffer entries with the entries in the state descriptor/thread array.

    Abstract translation: 计算机系统具有支持虚拟寻址的物理处理器。 虚拟处理器表示多个执行线程，并且当虚拟处理器从物理处理器之一移除时，虚拟处理器的所有线程的逻辑状态被存储在主存储器中的状态描述符字段中。 每个线程已经分配了线程标识符，该标识符在相应的虚拟处理器中是唯一的，并且每个虚拟处理器已经分配了唯一的状态描述符标识符。 存储多个虚拟处理器在其各自的线程标识符和状态描述符标识符下的线程的地址转换，并且当创建翻译后备缓冲器中的条目时生成序列号。 序列号与相应的线程标识符，状态描述符标识符和相应的翻译后备缓冲器条目中的有效位一起存储。 通过将转换后备缓冲器条目与状态描述符/线程数组中的条目进行比较，确定地址转换是否存储在当前线程标识符的翻译后备缓冲器中以及当前状态描述符标识符。

    Multi-engine address translation facility
    5.
    发明授权
    Multi-engine address translation facility 有权

    公开(公告)号：US10380032B2

    公开(公告)日：2019-08-13

    申请号：US15454243

    申请日：2017-03-09

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Uwe Brandt ,  Markus Helms ,  Christian Jacobi ,  Markus Kaltenbach ,  Thomas Koehler ,  Frank Lehnert

    IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/455

    Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

    Updating of shadow registers in N:1 clock domain
    7.
    发明授权
    Updating of shadow registers in N:1 clock domain 有权

    公开(公告)号：US09658852B2

    公开(公告)日：2017-05-23

    申请号：US14800136

    申请日：2015-07-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Thomas Koehler ,  Frank Lehnert

    IPC: G06F3/06 ,  G06F9/30

    CPC classification number: G06F9/30116 ,  G06F9/30123 ,  G06F9/30138 ,  G06F9/3863 ,  G06F9/3869

    Abstract: A processing unit includes a first storage entity being updated at a first clock cycle (CLK1) for holding a master copy of processing unit state. The processing unit further includes at least two shadow storage entities being updated with update information of the first storage entity. A shadow storage entity running at a second clock cycle (CLK2) is slower than the first clock cycle (CLK1). The first storage entity is coupled with the shadow storage entities via an intermediate storage entity, and the intermediate storage entity provides multiple storage stages for buffering consecutive update information of the first storage entity. Selection circuitry is adapted to provide one update information contained in one storage stage to the shadow storage entity with the active clock edge of the second clock cycle (CLK2) in order to update said shadow storage entity.

    Multi-engine address translation facility
    9.
    发明授权
    Multi-engine address translation facility 有权

    公开(公告)号：US10380033B2

    公开(公告)日：2019-08-13

    申请号：US15798585

    申请日：2017-10-31

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Uwe Brandt ,  Markus Helms ,  Christian Jacobi ,  Markus Kaltenbach ,  Thomas Koehler ,  Frank Lehnert

    IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/455

    Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

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