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    DYNAMIC DETECTION AND SOFTWARE CORRECTION OF INCORRECT LOCK AND ATOMIC UPDATE HINT BITS
    3.
    发明申请
    DYNAMIC DETECTION AND SOFTWARE CORRECTION OF INCORRECT LOCK AND ATOMIC UPDATE HINT BITS 审中-公开
    不正确锁定和原子更新提示位置的动态检测和软件校正

    公开(公告)号：US20160364332A1

    公开(公告)日：2016-12-15

    申请号：US14735429

    申请日：2015-06-10

    Applicant: International Business Machines Corporation

    Inventor： Benjamin Carter Nowak ,  Guy Lynn Guthrie ,  Venkat R. Indukuru

    IPC: G06F12/08

    CPC classification number: G06F9/00 ,  G06F11/00 ,  G06F11/073 ,  G06F11/0793

    Abstract: A hint bit detection and correction method uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.

    Abstract translation: 提示位检测和校正方法使用两个附加位作为每个缓存目录的一部分。 这些位表示lwarx和stwcx指令（larx disp，stcx disp）。 当出现提示位事件时，根据这两个位的组合，可能会显示一个提示位错误。 一旦检测到提示位错误，就会发出软件中断，提示位校正方法识别和纠正不正确的提示位。

    Dynamic detection and software correction of incorrect lock and atomic update hint bits
    4.
    发明授权
    Dynamic detection and software correction of incorrect lock and atomic update hint bits 有权
    不正确的锁定和原子更新提示位的动态检测和软件校正

    公开(公告)号：US09514046B1

    公开(公告)日：2016-12-06

    申请号：US14735429

    申请日：2015-06-10

    Applicant: International Business Machines Corporation

    Inventor： Benjamin Carter Nowak ,  Guy Lynn Guthrie ,  Venkat R. Indukuru

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F9/00 ,  G06F11/00 ,  G06F11/073 ,  G06F11/0793

    Abstract: A hint bit detection and correction method uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.

    Abstract translation: 提示位检测和校正方法使用两个附加位作为每个缓存目录的一部分。 这些位表示lwarx和stwcx指令（larx disp，stcx disp）。 当出现提示位事件时，根据这两个位的组合，可能会显示一个提示位错误。 一旦检测到提示位错误，就会发出软件中断，提示位校正方法识别和纠正不正确的提示位。

    BIDIRECTIONAL COUNTING OF DUAL OUTCOME EVENTS
    5.
    发明申请
    BIDIRECTIONAL COUNTING OF DUAL OUTCOME EVENTS 有权
    双向比较活动的双向计数

    公开(公告)号：US20140282616A1

    公开(公告)日：2014-09-18

    申请号：US13833776

    申请日：2013-03-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Giles Roger Frazier ,  Venkat R. Indukuru

    IPC: G06F9/54

    CPC classification number: G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

    Abstract: A dual outcome event monitoring unit comprises a plurality of inputs, and a first counter. Each input is associated with an event and the first counter is a bidirectional counter. The dual outcome event monitoring unit is configured to increment the first counter in response to receiving an indication of the occurrence of a first event of a plurality of events. The first event is designated as an increment event. The dual outcome event monitoring unit is also configured to decrement the first counter responsive to receiving an indication of the occurrence of a second event of a plurality of events. The second event is designated as a decrement event.

    Abstract translation: 双重结果事件监控单元包括多个输入和第一计数器。 每个输入与事件相关联，第一个计数器是一个双向计数器。 双重结果事件监控单元被配置为响应于接收到多个事件的第一事件的发生的指示而递增第一计数器。 第一个事件被指定为一个增量事件。 双重结果事件监控单元还被配置为响应于接收到多个事件的第二事件的发生的指示而递减第一计数器。 第二个事件被指定为递减事件。

    IDENTIFYING LOAD-HIT-STORE CONFLICTS
    6.
    发明申请
    IDENTIFYING LOAD-HIT-STORE CONFLICTS 有权
    识别负荷 - 存储冲突

    公开(公告)号：US20140108770A1

    公开(公告)日：2014-04-17

    申请号：US14109996

    申请日：2013-12-18

    Applicant: International Business Machines Corporation

    Inventor： Venkat R. Indukuru ,  Alexander E. Mericas ,  Satish K. Sadasivam ,  Madhavi G. Valluri

    IPC: G06F9/445

    CPC classification number: G06F9/44552 ,  G06F9/3834

    Abstract: A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.

    Abstract translation: 计算设备识别导致加载命中 - 存储冲突的加载指令和存储指令对。 处理器标记指示处理器从存储器加载第一数据集的第一加载指令。 处理器将特定目的寄存器中的第一加载指令所在的地址存储在存储器中。 处理器确定第一个加载指令与第一个存储指令的加载命中 - 存储冲突的位置。 如果处理器确定第一加载指令具有与第一存储指令的加载命中存储冲突，则处理器将第一数据集所在的地址存储在第二专用寄存器中的存储器中，对存储的第一数据集进行标记 通过第一存储指令，将第一存储指令所在的地址存储在第三专用寄存器中，并增加冲突计数器。

    Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall
    10.
    发明授权
    Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall 有权
    在流水线停止期间确定一组指令内每个停顿的指令的每个失速原因

    公开(公告)号：US09495170B2

    公开(公告)日：2016-11-15

    申请号：US14102807

    申请日：2013-12-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Venkat R. Indukuru ,  Brian R. Konigsburg ,  Alexander E. Mericas ,  Benjamin W. Stolt

    IPC: G06F9/38

    CPC classification number: G06F9/3867 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857

    Abstract: During a pipeline stall in a processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from functional units of the processor, finish reports including completion reasons for separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the finish reports. Once the monitoring unit receives a complete indicator from the completion unit, indicating the completion of the next to complete instruction group, the monitoring unit stores each determined stall reason aligned with each next to finish indicator in memory.

    Abstract translation: 在处理器中的流水线停止期间，直到完成指令组的下一个完成，监视单元从处理器的完成单元接收到指示从多个指令中指出最早的未完成指令的完成的完成指示符 的一个完整的指导组。 监视单元从处理器的功能单元接收完成报告，包括单独指令的完成原因。 从完成原因的选择中，从完成报告中的与下一个完成指示符对齐的完成报告的选择中，监视单元从最多的指令的多个失败原因中确定至少一个失败原因。 一旦监视单元从完成单元接收到完整的指示符，指示完成下一个完成指令组，则监视单元将每个确定的停顿原因与每个下一个完成指示符对准在存储器中。

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