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    Buffer Addressing for a Convolutional Neural Network
    3.
    发明申请
    Buffer Addressing for a Convolutional Neural Network 有权

    公开(公告)号：US20220383067A1

    公开(公告)日：2022-12-01

    申请号：US17868675

    申请日：2022-07-19

    Applicant: Imagination Technologies Limited

    Inventor： Daniel Barnard ,  Clifford Gibson ,  Colin McQuillan

    IPC: G06N3/04 ,  G06F12/02 ,  G06N3/063 ,  G06F12/06

    Abstract: A method for providing input data for a layer of a convolutional neural network “CNN”, the method comprising: receiving input data comprising input data values to be processed in a layer of the CNN; determining addresses in banked memory of a buffer in which the received data values are to be stored based upon format data indicating a format parameter of the input data in the layer and indicating a format parameter of a filter which is to be used to process the input data in the layer; and storing the received input data values at the determined addresses in the buffer for retrieval for processing in the layer.

    Hardware implementation of convolutional layer of deep neural network
    4.
    发明授权
    Hardware implementation of convolutional layer of deep neural network 有权

    公开(公告)号：US11157592B2

    公开(公告)日：2021-10-26

    申请号：US17165014

    申请日：2021-02-02

    Applicant: Imagination Technologies Limited

    Inventor： Chris Martin ,  David Hough ,  Clifford Gibson ,  Daniel Barnard

    IPC: G06F17/15 ,  G06N3/063 ,  G06F7/544 ,  G06N3/04

    Abstract: Hardware implementations of, and methods for processing, a convolution layer of a DNN that comprise a plurality of convolution engines wherein the input data and weights are provided to the convolution engines in an order that allows input data and weights read from memory to be used in at least two filter-window calculations performed either by the same convolution engine in successive cycles or by different convolution engines in the same cycle. For example, in some hardware implementations of a convolution layer the convolution engines are configured to process the same weights but different input data each cycle, but the input data for each convolution engine remains the same for at least two cycles so that the convolution engines use the same input data in at least two consecutive cycles.

    INTERSECTION TESTING FOR RAY TRACING
    6.
    发明公开
    INTERSECTION TESTING FOR RAY TRACING 审中-公开

    公开(公告)号：US20240169656A1

    公开(公告)日：2024-05-23

    申请号：US18426273

    申请日：2024-01-29

    Applicant: Imagination Technologies Limited

    Inventor： Daniel Barnard

    IPC: G06T15/06 ,  G06T15/00

    CPC classification number: G06T15/06 ,  G06T15/005 ,  G06T2200/28 ,  G06T2210/12 ,  G06T2210/21

    Abstract: A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements for intersection testing. The system defines and updates progress information that identifies, for a ray, leaf nodes of the hierarchical acceleration structure which identify elements for which it is not yet known whether or not the ray interests.

    INTERSECTION TESTING FOR RAY TRACING
    7.
    发明公开
    INTERSECTION TESTING FOR RAY TRACING 审中-公开

    公开(公告)号：US20240144582A1

    公开(公告)日：2024-05-02

    申请号：US18407201

    申请日：2024-01-08

    Applicant: Imagination Technologies Limited

    Inventor： Daniel Barnard

    IPC: G06T15/06 ,  G06T17/00

    CPC classification number: G06T15/06 ,  G06T17/005 ,  G06T2210/21 ,  G06T2210/52

    Abstract: A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements able to be intersected by a ray. The system makes use of a serial-mode ray intersection process, in which, when a ray intersects a bounding volume, a limited number of new ray requests are generated.

    METHODS AND HARDWARE LOGIC FOR LOADING RAY TRACING DATA INTO A SHADER PROCESSING UNIT OF A GRAPHICS PROCESSING UNIT
    10.
    发明公开
    METHODS AND HARDWARE LOGIC FOR LOADING RAY TRACING DATA INTO A SHADER PROCESSING UNIT OF A GRAPHICS PROCESSING UNIT 审中-公开

    公开(公告)号：US20230334750A1

    公开(公告)日：2023-10-19

    申请号：US18126462

    申请日：2023-03-26

    Applicant: Imagination Technologies Limited

    Inventor： Daniel Barnard

    IPC: G06T15/00 ,  G06T1/20 ,  G06T15/06

    CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T15/06

    Abstract: Shader processing units for a graphics processing unit that are configured to execute one or more ray tracing shaders that process ray data associated with one or more rays. The ray data for a ray includes a plurality of ray data elements. The shader processing unit comprises storage, and load logic. The load logic is configured to receive, as part of a ray tracing shader, a ray load instruction that comprises: (i) information identifying a load group of a plurality of load groups, each load group of the plurality of load groups comprising one or more ray data elements of the plurality of ray data elements, and (ii) information identifying one or more ray data elements of the identified load group to be retrieved from an external unit. In response to the ray load instruction, the load logic sends one or more load requests to the external unit which cause the external unit to retrieve the identified ray data elements of the identified load group for one or more rays. The received ray data elements are then stored in the storage of the shader processing unit for processing by the ray tracing shader.

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