公开(公告)号：US20250062776A1

公开(公告)日：2025-02-20

申请号：US18937961

申请日：2024-11-05

Applicant: Imagination Technologies Limited

Inventor： Peter Malcolm Lacey ,  Simon Fenney

IPC: H03M7/30 ,  H04N19/13 ,  H04N19/132 ,  H04N19/176 ,  H04N19/186

Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.

公开(公告)号：US20240331298A1

公开(公告)日：2024-10-03

申请号：US18736313

申请日：2024-06-06

Applicant: Imagination Technologies Limited

Inventor： Peter Malcolm Lacey

IPC: G06T17/20 ,  G06T15/00 ,  G06T17/00 ,  G06T17/10

CPC classification number: G06T17/20 ,  G06T15/005 ,  G06T17/005 ,  G06T17/10 ,  G06T2200/28

Abstract: A method of generating identifiers (IDs) for primitives and optionally vertices during tessellation. The IDs include a binary sequence of bits that represents the sub-division steps taken during the tessellation process and so encodes the way in which tessellation has been performed. Such an ID may subsequently be used to generate a random primitive or vertex and hence recalculate vertex data for that primitive or vertex.

公开(公告)号：US12039667B2

公开(公告)日：2024-07-16

申请号：US16376511

申请日：2019-04-05

Applicant: Imagination Technologies Limited

Inventor： Peter Malcolm Lacey

IPC: G06T17/20 ,  G06T15/00 ,  G06T17/00 ,  G06T17/10

CPC classification number: G06T17/20 ,  G06T15/005 ,  G06T17/005 ,  G06T17/10 ,  G06T2200/28

Abstract: A method of generating identifiers (IDs) for primitives and optionally vertices during tessellation. The IDs include a binary sequence of bits that represents the sub-division steps taken during the tessellation process and so encodes the way in which tessellation has been performed. Such an ID may subsequently be used to generate a random primitive or vertex and hence recalculate vertex data for that primitive or vertex.

公开(公告)号：US12034934B2

公开(公告)日：2024-07-09

申请号：US18123148

申请日：2023-03-17

Applicant: Imagination Technologies Limited

Inventor： Ilaria Martinelli ,  Jeff Bond ,  Simon Fenney ,  Peter Malcolm Lacey ,  Gregory Clark

IPC: H04N19/00 ,  G06T1/20 ,  H04N19/132 ,  H04N19/176 ,  H04N19/42 ,  H04N19/89

CPC classification number: H04N19/132 ,  G06T1/20 ,  H04N19/176 ,  H04N19/42 ,  H04N19/89

Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.

公开(公告)号：US20240135648A1

公开(公告)日：2024-04-25

申请号：US18519632

申请日：2023-11-27

Applicant: Imagination Technologies Limited

Inventor： Peter Malcolm Lacey ,  Simon Fenney

IPC: G06T17/20 ,  G06T15/00

CPC classification number: G06T17/20 ,  G06T15/005 ,  G06T17/205

Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.

公开(公告)号：US20220392139A1

公开(公告)日：2022-12-08

申请号：US17881757

申请日：2022-08-05

Applicant: Imagination Technologies Limited

Inventor： Peter Malcolm Lacey

IPC: G06T15/00 ,  G06T17/20

Abstract: A method of controlling the order in which primitives, generated during tessellation, are output by the tessellation unit involves sub-dividing a patch, selecting one of the two sub-patches which are formed by the sub-division and tessellating that sub-patch until no further sub-division is possible before tessellating the other (non-selected) sub-patch. The method is recursively applied at each level of sub-division. Patches are output as primitives at the point in the method where they do not require any further sub-division. The selection of a sub-patch is made based on the values of one or more flags and any suitable tessellation method may be used to determine whether to sub-divide a patch. Methods of controlling the order in which vertices are output by the tessellation unit are also described and these may be used in combination with, or independently of, the method of controlling the primitive order.

公开(公告)号：US11501494B2

公开(公告)日：2022-11-15

申请号：US17061721

申请日：2020-10-02

Applicant: Imagination Technologies Limited

Inventor： Peter Malcolm Lacey ,  Simon Fenney

IPC: G06T17/20 ,  G06T15/00 ,  G06T15/80

Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.

公开(公告)号：US20220270325A1

公开(公告)日：2022-08-25

申请号：US17733847

申请日：2022-04-29

Applicant: Imagination Technologies Limited

Inventor： Peter Malcolm Lacey ,  Simon Fenney

IPC: G06T17/20 ,  G06T1/20 ,  G06T15/00 ,  G06T17/10

Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.

公开(公告)号：US20210019940A1

公开(公告)日：2021-01-21

申请号：US17061721

申请日：2020-10-02

Applicant: Imagination Technologies Limited

Inventor： Peter Malcolm Lacey ,  Simon Fenney

IPC: G06T17/20 ,  G06T15/00 ,  G06T15/80

Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.

公开(公告)号：US10783705B2

公开(公告)日：2020-09-22

申请号：US16123544

申请日：2018-09-06

Applicant: Imagination Technologies Limited

Inventor： Peter Malcolm Lacey ,  Simon Fenney

IPC: G06T17/20 ,  G06T15/00

Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.