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公开(公告)号：US20240402991A1
公开(公告)日：2024-12-05
申请号：US18799336
申请日：2024-08-09
Applicant: Imagination Technologies Limited
Inventor： Thomas Rose
Abstract: A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m−r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m−r−1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m−r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.
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公开(公告)号：US20230030495A1
公开(公告)日：2023-02-02
申请号：US17853694
申请日：2022-06-29
Applicant: Imagination Technologies Limited
Inventor： Thomas Rose , Sam Elliott
IPC: G06F7/52
Abstract: A fixed logic circuit configured to perform a multiplication operation a*x, where a is an integer constant, x is an integer variable in the range 0 to 2m−1, and m is a positive integer. The fixed logic circuit includes division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation: └2ix/q┘ where q,i are selected such that: a*x=└2ix/q┘ Multiplication logic determines a predetermined number of one or more least significant bits of the result of the multiplication operation a*x; and output logic combines the predetermined number of one or more most significant bits of the result of the division operation with the predetermined number of one or more least significant bits of the result of the multiplication operation so as to provide an output for the multiplication operation a*x.
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公开(公告)号：US11429389B2
公开(公告)日：2022-08-30
申请号：US17104940
申请日：2020-11-25
Applicant: Imagination Technologies Limited
Inventor： Simon Nield , Thomas Rose
Abstract: A method for a plurality of pipelines, each having a processing element having first and second inputs and first and second lines, wherein at least one of the pipelines includes first and second logic operable to select a respective line so that data is received at the first and second inputs respectively. A first mode is selected and for the at least one pipeline, the first and second lines of that pipeline are selected such that the processing element of that pipeline receives data via the first and second lines of that pipeline, the first line being capable of supplying data that is different to the second line. A second mode is selected and for the at least one pipeline a line of another pipeline is selected, the second line of the at least one pipeline is selected and the same data at the second line is supplied as the first line.
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公开(公告)号：US20210081205A1
公开(公告)日：2021-03-18
申请号：US17104940
申请日：2020-11-25
Applicant: Imagination Technologies Limited
Inventor： Simon Nield , Thomas Rose
Abstract: A method for a plurality of pipelines, each having a processing element having first and second inputs and first and second lines, wherein at least one of the pipelines includes first and second logic operable to select a respective line so that data is received at the first and second inputs respectively. A first mode is selected and for the at least one pipeline, the first and second lines of that pipeline are selected such that the processing element of that pipeline receives data via the first and second lines of that pipeline, the first line being capable of supplying data that is different to the second line. A second mode is selected and for the at least one pipeline a line of another pipeline is selected, the second line of the at least one pipeline is selected and the same data at the second line is supplied as the first line.
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公开(公告)号：US10372420B2
公开(公告)日：2019-08-06
申请号：US15149312
申请日：2016-05-09
Applicant: Imagination Technologies Limited
Inventor： Thomas Rose
IPC: G06F7/72
Abstract: A binary logic circuit for determining y=x mod(2m−1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer β and a second m-bit integer γ; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by β; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by γ; and the binary value 1.
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Patent Agency Ranking
公开(公告)号：US10235136B2
公开(公告)日：2019-03-19
申请号：US15606351
申请日：2017-05-26
Applicant: Imagination Technologies Limited
Inventor： Thomas Rose
Abstract: A binary logic circuit is provided for determining a rounded value of px q , where p and q are coprime constant integers with p
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公开(公告)号：US20230376275A1
公开(公告)日：2023-11-23
申请号：US18072356
申请日：2022-11-30
Applicant: Imagination Technologies Limited
Inventor： Thomas Rose
CPC classification number: G06F7/57 , G06F7/5443
Abstract: A hardware representation of a fixed logic circuit is derived for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode, where p, q are coprime integers, and x is an m-bit input. An infinite CSD expansion of the rational p/q is determined, a truncated summation array of the bits of the CSD expansion of the rational p/q operating on the bits of the input x is formed by discarding at least the kth column of the array below the position of the binary point, where k=└ ln2(mq)┘+1; further truncating the truncated summation array whilst ensuring that
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公开(公告)号：US20230229397A1
公开(公告)日：2023-07-20
申请号：US18072463
申请日：2022-11-30
Applicant: Imagination Technologies Limited
Inventor： Thomas Rose
IPC: G06F7/544 , G06F7/499 , G06F30/392
CPC classification number: G06F7/5443 , G06F7/49947 , G06F30/392
Abstract: A fixed logic circuit for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode. Fixed logic hardware is derived comprising an addition array configured to operate on canonical signed digit (CSD) forms of binary values (a CSD array) so as to form an approximation of a multiplication of an input x [m−1:0] by a rational p/q. A truncated summation array of a finite sequence of most significant bits of an infinite CSD expansion of the rational p/q operating on the bits of the input x satisfies
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公开(公告)号：US11422802B2
公开(公告)日：2022-08-23
申请号：US16725378
申请日：2019-12-23
Applicant: Imagination Technologies Limited
Inventor： Thomas Rose , Max Freiburghaus , Robert McKemey
Abstract: A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by 1 / d i . The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.
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公开(公告)号：US20190311519A1
公开(公告)日：2019-10-10
申请号：US16369978
申请日：2019-03-29
Applicant: Imagination Technologies Limited
Inventor： Thomas Rose
Abstract: A texture filtering unit has inputs arranged to receive at least two texture values each clock cycle and a plurality of filter coefficients, the plurality of filter coefficients relating to a plurality of different texture filtering methods; hardware logic arranged to convert the input texture values to fixed-point representation; a coefficient merging logic block arranged to generate a single composite filter coefficient for each input texture value from the plurality of filter coefficients; one multiplier for each input texture value, wherein each multiplier is arranged to multiply one of the input texture values by its corresponding single composite filter coefficient; an addition unit arranged to add together outputs from each of the multipliers; hardware logic arranged to convert an output from the addition unit back to floating-point format; and an output arranged to output the converted output from the addition unit.
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