公开(公告)号：US11908694B2

公开(公告)日：2024-02-20

申请号：US17127309

申请日：2020-12-18

Applicant: Infineon Technologies AG

Inventor： Moriz Jelinek ,  Michael Hell ,  Caspar Leendertz ,  Kristijan Luka Mletschnig ,  Hans-Joachim Schulze

IPC: H01J37/317 ,  H01L21/265 ,  H01L21/04 ,  H01L29/36

CPC classification number: H01L21/26586 ,  H01J37/3171 ,  H01L21/046 ,  H01L21/047 ,  H01L21/265 ,  H01L21/2652 ,  H01L29/36 ,  H01J2237/24578 ,  H01J2237/31703

Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.

公开(公告)号：US20230253454A1

公开(公告)日：2023-08-10

申请号：US18100144

申请日：2023-01-23

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Thomas Ralf Siemieniec ,  Werner Schustereder ,  Kristijan Luka Mletschnig ,  Axel König

IPC: H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/0869 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/7813 ,  H01L21/0475 ,  H01L21/0485 ,  H01L29/66068

Abstract: A method of manufacturing a semiconductor device includes forming a trench that extends from a first surface into a silicon carbide body. A first doped region and an oppositely doped second doped region are formed in the silicon carbide body. A lower layer structure is formed on a lower sidewall portion of the trench. An upper layer stack is formed on an upper sidewall portion and/or on the first surface. The first doped region and the upper layer stack are in direct contact along the upper sidewall portion and/or on the first surface. The second doped region and the lower layer structure are in direct contact along the lower sidewall portion.

公开(公告)号：US20250014902A1

公开(公告)日：2025-01-09

申请号：US18754277

申请日：2024-06-26

Applicant: Infineon Technologies AG

Inventor： Axel König ,  Kristijan Luka Mletschnig ,  Andreas Vörckel ,  Caspar Leendertz ,  Werner Schustereder ,  Hans-Joachim Schulze

IPC: H01L21/04 ,  H01L21/02 ,  H01L21/324

Abstract: A method of manufacturing a semiconductor device includes forming a doped region in a semiconductor body. Forming the doped region includes: introducing first dopants through a first surface of the semiconductor body at a first vertical reference level by a first ion implantation process; thereafter, applying a first heat treatment to the semiconductor body; and thereafter, introducing second dopants through the first surface of the semiconductor body at the first vertical reference level by a second ion implantation process. An atomic number of the first dopants is equal to an atomic number of the second dopants. An ion implantation energy of the second ion implantation process differs by less than 20% from an ion implantation energy of the first ion implantation process. An ion implantation dose of the second ion implantation process differs by less than 20% from an ion implantation dose of the first ion implantation process.