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公开(公告)号:US20220059180A1
公开(公告)日:2022-02-24
申请号:US17387189
申请日:2021-07-28
Applicant: Infineon Technologies AG
Inventor: Martin Perner
Abstract: A method for testing a memory area. The method includes jumping from a destination address to a source address, reading a data word at the source address after jumping to the source address, and examining the data word. The source address was determined based on a static test.
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2.
公开(公告)号:US11238948B2
公开(公告)日:2022-02-01
申请号:US17168310
申请日:2021-02-05
Applicant: Infineon Technologies AG
Inventor: Martin Perner
Abstract: A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells. The processor is configured to test memory cells of a protected memory area of the memory by performing memory accesses at bit level, control a counting register in such a way that a value stored in the counting register is modified according to a number of performed memory accesses, and test memory cells of the protected memory area of the memory only if the value stored in the counting register lies within a permissible value range.
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公开(公告)号:US09941000B2
公开(公告)日:2018-04-10
申请号:US15282231
申请日:2016-09-30
Applicant: Infineon Technologies AG
Inventor: Martin Perner
CPC classification number: G11C11/5642 , G06F11/1068 , G06F11/2094 , G06F2201/82 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C29/52 , G11C2211/5641
Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.
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公开(公告)号:US20180358089A1
公开(公告)日:2018-12-13
申请号:US16108243
申请日:2018-08-22
Applicant: Infineon Technologies AG
Inventor: Martin Perner
CPC classification number: G11C11/5642 , G06F11/1068 , G06F11/2094 , G06F2201/82 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C29/52 , G11C2211/5641
Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.
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公开(公告)号:US20180226124A1
公开(公告)日:2018-08-09
申请号:US15949480
申请日:2018-04-10
Applicant: Infineon Technologies AG
Inventor: Martin Perner
CPC classification number: G11C11/5642 , G06F11/1068 , G06F11/2094 , G06F2201/82 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C29/52 , G11C2211/5641
Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.
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6.
公开(公告)号:US20210158882A1
公开(公告)日:2021-05-27
申请号:US17168310
申请日:2021-02-05
Applicant: Infineon Technologies AG
Inventor: Martin Perner
Abstract: A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells. The processor is configured to test memory cells of a protected memory area of the memory by performing memory accesses at bit level, control a counting register in such a way that a value stored in the counting register is modified according to a number of performed memory accesses, and test memory cells of the protected memory area of the memory only if the value stored in the counting register lies within a permissible value range
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公开(公告)号:US10083743B2
公开(公告)日:2018-09-25
申请号:US15949480
申请日:2018-04-10
Applicant: Infineon Technologies AG
Inventor: Martin Perner
CPC classification number: G11C11/5642 , G06F11/1068 , G06F11/2094 , G06F2201/82 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C29/52 , G11C2211/5641
Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.
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8.
公开(公告)号:US10916322B2
公开(公告)日:2021-02-09
申请号:US16109185
申请日:2018-08-22
Applicant: Infineon Technologies AG
Inventor: Martin Perner
Abstract: A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells. The processor is configured to test memory cells of a protected memory area of the memory by performing memory accesses at bit level, control a counting register in such a way that a value stored in the counting register is modified according to a number of performed memory accesses, and test memory cells of the protected memory area of the memory only if the value stored in the counting register lies within a permissible value range.
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公开(公告)号:US10395729B2
公开(公告)日:2019-08-27
申请号:US16108243
申请日:2018-08-22
Applicant: Infineon Technologies AG
Inventor: Martin Perner
Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.
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公开(公告)号:US11742048B2
公开(公告)日:2023-08-29
申请号:US17387189
申请日:2021-07-28
Applicant: Infineon Technologies AG
Inventor: Martin Perner
Abstract: A method for testing a memory area. The method includes jumping from a destination address to a source address, reading a data word at the source address after jumping to the source address, and examining the data word. The source address was determined based on a static test.
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