公开(公告)号：US20150115458A1

公开(公告)日：2015-04-30

申请号：US14064093

申请日：2013-10-25

Applicant: Infineon Technologies AG

Inventor： Petteri PALM

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/89 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/24 ,  H01L24/31 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05018 ,  H01L2224/08112 ,  H01L2224/08137 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/80031 ,  H01L2224/80488 ,  H01L2224/80801 ,  H01L2224/8082 ,  H01L2224/8085 ,  H01L2224/80904 ,  H01L2224/8203 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/83851 ,  H01L2224/83889 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

Abstract translation: 一种器件包括包括第一面的第一半导体芯片，其中第一接触焊盘布置在第一面上。 该器件还包括第二半导体芯片，其包括第一面，其中第一接触焊盘布置在第一面上，其中第一半导体芯片和第二半导体芯片布置成使得第一半导体芯片的第一面朝向 第一方向和第二半导体芯片的第一面朝向与第一方向相反的第二方向。 第一半导体芯片位于第二半导体芯片的外形的横向外侧。

公开(公告)号：US20220238481A1

公开(公告)日：2022-07-28

申请号：US17722929

申请日：2022-04-18

Applicant: Infineon Technologies AG

Inventor： Petteri PALM ,  Thorsten SCHARF ,  Ralf WOMBACHER

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/78 ,  H01L23/055 ,  H01L23/48 ,  H01L21/48

Abstract: An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

公开(公告)号：US20230164911A1

公开(公告)日：2023-05-25

申请号：US17989228

申请日：2022-11-17

Applicant: Infineon Technologies AG

Inventor： Mahadi-Ul HASSAN ,  Petteri PALM ,  Thomas GEBHARD

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/18

CPC classification number: H05K1/0259 ,  H05K3/4655 ,  H05K1/185 ,  H05K2201/10166

Abstract: A printed circuit board and method of manufacturing a printed circuit board are disclosed. In one example, the method comprises embedding an electronic component in a laminate, and protecting the electronic component against electrostatic discharge during at least part of the manufacturing process by an electrically conductive electrostatic discharge protection structure integrated in the laminate and connected to the electronic component.

公开(公告)号：US20220122906A1

公开(公告)日：2022-04-21

申请号：US17485742

申请日：2021-09-27

Applicant: Infineon Technologies AG

Inventor： Sergey YUFEREV ,  Paul Armand Asentista CALO ,  Theng Chao LONG ,  Josef MAERZ ,  Chee Yang NG ,  Petteri PALM ,  Wae Chet YONG

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/00

Abstract: A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.

公开(公告)号：US20240021512A1

公开(公告)日：2024-01-18

申请号：US18374107

申请日：2023-09-28

Applicant: Infineon Technologies AG

Inventor： Petteri PALM

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L23/49844 ,  H01L24/20 ,  H01L24/04 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/96 ,  H01L24/19 ,  H01L24/05 ,  H01L2221/68372 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2221/68359

Abstract: A die package and method is disclosed. In one example, the die package includes a die having a first die contact on a first side and a second die contact on a second side opposite the first side, and insulating material laterally adjacent to the die. A metal structure substantially directly contacts the surface of the second die contact, wherein the metal structure is made of the same material as the second die contact. A first pad contact on the first side of the die electrically contacts the first die contact, and a second pad contact on the first side of the die electrically contacts the second die contact via the metal structure. The insulating material electrically insulates the metal structure from the first die contact.

公开(公告)号：US20220399262A1

公开(公告)日：2022-12-15

申请号：US17849788

申请日：2022-06-27

Applicant: Infineon Technologies AG

Inventor： Petteri PALM

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

Abstract: A die package and method is disclosed. In one example, the die package includes a die having a first die contact on a first side and a second die contact on a second side opposite the first side, and insulating material laterally adjacent to the die. A metal structure substantially directly contacts the surface of the second die contact, wherein the metal structure is made of the same material as the second die contact. A first pad contact on the first side of the die electrically contacts the first die contact, and a second pad contact on the first side of the die electrically contacts the second die contact via the metal structure. The insulating material electrically insulates the metal structure from the first die contact.

公开(公告)号：US20220377901A1

公开(公告)日：2022-11-24

申请号：US17737314

申请日：2022-05-05

Applicant: Infineon Technologies AG

Inventor： Tomasz NAEVE ,  Urban MEDIC ,  Milad MOSTOFIZADEH ,  Petteri PALM

IPC: H05K1/18 ,  H05K1/02

Abstract: An electronic device is disclosed. In one example, the electronic device comprises a carrier board, a metal inlay having a cavity and being arranged in the carrier board. At least one electronic component is arranged at least partially in the cavity and embedded in the carrier board. Electric contacts are located at a castellated edge of the carrier board.

公开(公告)号：US20210287964A1

公开(公告)日：2021-09-16

申请号：US17196652

申请日：2021-03-09

Applicant: Infineon Technologies AG

Inventor： Petteri PALM ,  Robert FEHLER ,  Josef HOEGLAUER ,  Angela KESSLER

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes a semiconductor chip including a first chip contact pad on a first chip main surface. The semiconductor device further includes a first electrically conductive layer arranged over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first electrically conductive layer extends in a direction parallel to the first chip main surface. An electrical through connection is electrically coupled to the first electrically conductive layer and to a second electrically conductive layer, wherein the electrical through connection extends in a direction perpendicular to the first chip main surface, and wherein, in a top view of the first chip main surface, the electrical through connection and the semiconductor chip are non-overlapping.

公开(公告)号：US20170278762A1

公开(公告)日：2017-09-28

申请号：US15468045

申请日：2017-03-23

Applicant: Infineon Technologies AG

Inventor： Angela KESSLER ,  Oliver HAEBERLEN ,  Matteo-Alessandro KUTSCHAK ,  Ralf OTREMBA ,  Petteri PALM ,  Boris PLIKAT ,  Thorsten SCHARF ,  Klaus SCHIESS ,  Fabian SCHNOY ,  Erich SYRI

IPC: H01L21/66 ,  H01L23/498 ,  G01N21/84 ,  H01L23/31

CPC classification number: H01L22/32 ,  G01N21/84 ,  G01N21/95684 ,  G01N2201/12 ,  H01L22/12 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/052 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1033

Abstract: A package comprising an electronic chip, a laminate type encapsulant in and/or on which the electronic chip is mounted, a solderable electric contact on a solder surface of the package, and a solder flow path on and/or in the package which is configured so that, upon soldering the electric contact with a mounting base, part of solder material flows along the solder flow path towards a surface of the package at which the solder material is optically inspectable after completion of the solder connection between the mounting base and the electric contact.

公开(公告)号：US20150221569A1

公开(公告)日：2015-08-06

申请号：US14613446

申请日：2015-02-04

Applicant: Infineon Technologies AG

Inventor： Petteri PALM ,  Thorsten SCHARF ,  Ralf WOMBACHER

IPC: H01L23/055 ,  H01L23/48 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L24/82 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/055 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/25 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/8285 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/82 ,  H01L2224/83

Abstract: Electronic module (100), which comprises a first substrate (102), a first dielectric layer (104) on the first substrate (102), at least one electronic chip (106), which is mounted with a first main surface (108) directly or indirectly on partial region of the first dielectric layer (104), a second substrate (110) over a second main surface (114) of the at least one electronic chip (106), and an electrical contacting (116) for the electric contact of the at least one electronic chip (106) through the first dielectric layer (104), wherein the first adhesion layer (104) on the first substrate (102) extends over an area, which exceeds the first main surface (108).

Abstract translation: 电子模块（100），其包括第一基板（102），第一基板（102）上的第一介电层（104），至少一个电子芯片（106），其安装有第一主表面（108） 直接或间接地在第一介电层（104）的部分区域上，在所述至少一个电子芯片（106）的第二主表面（114）上方的第二基板（110）以及用于电气 所述至少一个电子芯片（106）通过所述第一介电层（104）的接触，其中所述第一基板（102）上的所述第一粘合层（104）延伸超过所述第一主表面（108）的区域。