PARTITIONING FORWARD ERROR CORRECTION DECODING ITERATIONS TO ACCOMMODATE MULTIPLE DATA STREAMS
    1.
    发明申请
    PARTITIONING FORWARD ERROR CORRECTION DECODING ITERATIONS TO ACCOMMODATE MULTIPLE DATA STREAMS 有权
    分段前向纠错修改迭代多个数据流的迭代

    公开(公告)号:US20150381315A1

    公开(公告)日:2015-12-31

    申请号:US14319354

    申请日:2014-06-30

    Abstract: An optical receiver may receive a data stream, and may decode the data stream using a first iterative forward error correction (FEC) decoder. The optical receiver may determine whether to further decode the data stream using the first iterative FEC decoder or a second iterative FEC decoder that is different from the first iterative FEC decoder. The optical receiver may selectively perform a first action or a section action based on determining whether to further decode the data stream. The first action may include providing the data stream to the first iterative FEC decoder or the second iterative FEC decoder for further decoding when the data stream is to be further decoded. The second action may include preventing the data stream from being provided to the first iterative FEC decoder or the second iterative FEC decoder when the data stream is not to be further decoded.

    Abstract translation: 光接收机可以接收数据流,并且可以使用第一迭代前向纠错(FEC)解码器对数据流进行解码。 光接收机可以使用不同于第一迭代FEC解码器的第一迭代FEC解码器或第二迭代FEC解码器来确定是否进一步解码数据流。 光接收机可以基于确定是否进一步解码数据流来选择性地执行第一动作或片段动作。 第一动作可以包括将数据流提供给第一迭代FEC解码器或第二迭代FEC解码器,用于在要进一步解码数据流时进一步解码。 第二动作可以包括当数据流不被进一步解码时,防止数据流被提供给第一迭代FEC解码器或第二迭代FEC解码器。

    CODE DESIGN AND HIGH-THROUGHPUT DECODER ARCHITECTURE FOR LAYERED DECODING OF A LOW-DENSITY PARITY-CHECK CODE
    2.
    发明申请
    CODE DESIGN AND HIGH-THROUGHPUT DECODER ARCHITECTURE FOR LAYERED DECODING OF A LOW-DENSITY PARITY-CHECK CODE 有权
    用于低密度奇偶校验代码的层次解码的代码设计和高速解码器架构

    公开(公告)号:US20150311919A1

    公开(公告)日:2015-10-29

    申请号:US14323635

    申请日:2014-07-03

    Abstract: A low-density parity-check (LDPC) decoder may receive LDPC coded data. The LDPC decoder may perform a decoding iteration associated with decoding the LDPC coded data. The decoding iteration may be performed by processing a group of layers. Each layer may include a corresponding set of check node elements, and may be processed by causing each check node element, of the set of check node elements corresponding to the layer, to update a set of variable node elements, connected to the check node element and associated with the LDPC coded data, based on a check node function associated with the check node element. The decoding iteration may be performed such that each layer is processed in parallel, and such that each check node element updates the corresponding set of variable node elements in parallel. The LDPC decoder may provide a result of performing the decoding iteration.

    Abstract translation: 低密度奇偶校验(LDPC)解码器可以接收LDPC编码数据。 LDPC解码器可以执行与解码LDPC编码数据相关联的解码迭代。 解码迭代可以通过处理一组层来执行。 每个层可以包括对应的一组校验节点元素,并且可以通过使与该层相对应的校验节点元素组的每个校验节点元素来更新连接到校验节点元素的一组变量节点元素 并且基于与所述校验节点元素相关联的校验节点功能与所述LDPC编码数据相关联。 可以执行解码迭代,使得每个层被并行处理,并且使得每个校验节点元素并行地更新相应的变量节点元素组。 LDPC解码器可以提供执行解码迭代的结果。

    EFFICIENT STORAGE ARCHITECTURE FOR LOW-DENSITY PARITY-CHECK DECODING
    3.
    发明申请
    EFFICIENT STORAGE ARCHITECTURE FOR LOW-DENSITY PARITY-CHECK DECODING 有权
    用于低密度奇偶校验解码的高效存储体系结构

    公开(公告)号:US20150311918A1

    公开(公告)日:2015-10-29

    申请号:US14319503

    申请日:2014-06-30

    Abstract: A low-density parity-check (LDPC) decoder may comprise a shift register configured to receive LDPC coded data, perform an iteration associated with decoding the LDPC coded data, and provide a result of performing the iteration. The shift register may include a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle, a quantity of stages corresponding to a quantity of clock cycles needed to perform the iteration, a quantity of storage elements, associated with storing the data words during the iteration, and a set of check node elements associated with updating the data words during the iteration. The quantity of stages times the quantity of lanes may be greater than the quantity of storage elements by a particular number of storage elements. The particular number of storage elements may be displaced by the set of check node elements.

    Abstract translation: 低密度奇偶校验(LDPC)解码器可以包括被配置为接收LDPC编码数据的移位寄存器,执行与解码LDPC编码数据相关联的迭代,并且提供执行迭代的结果。 移位寄存器可以包括对应于在特定时钟周期由移位寄存器接收的数据量的量的通道数量,对应于执行迭代所需的时钟周期量的级数,存储元件的数量, 与在迭代期间存储数据字相关联,以及与在迭代期间更新数据字相关联的一组校验节点元素。 阶段数乘以车道数量可能大于存储元件数量的特定数量的存储元件。 存储元件的特定数量可以被该组校验节点元素置换。

    FREQUENCY AND PHASE COMPENSATION FOR MODULATION FORMATS USING MULTIPLE SUB-CARRIERS
    4.
    发明申请
    FREQUENCY AND PHASE COMPENSATION FOR MODULATION FORMATS USING MULTIPLE SUB-CARRIERS 有权
    使用多个子载波的调制格式的频率和相位补偿

    公开(公告)号:US20150280834A1

    公开(公告)日:2015-10-01

    申请号:US14231357

    申请日:2014-03-31

    CPC classification number: H04B10/6164 H04B10/611 H04B10/6165 H04J14/02

    Abstract: An optical receiver may receive input signals carried by respective sub-carriers. The optical receiver may determine, based on the input signals, a compensation value to be used to modify an input signal. The optical receiver may use the compensation value to adjust the input signal to form a modified input signal. The compensation value may be used to modify a frequency or a phase of the input signal. The optical receiver may determine, based on the modified input signal, a phase estimate value that represents an estimated phase associated with the input signal. The optical receiver may combine the compensation value and the phase estimate value to form a phase adjustment signal, may combine the input signal and the phase adjustment signal to form an output signal, and may output the output signal.

    Abstract translation: 光接收机可以接收由各个子载波承载的输入信号。 光接收机可以基于输入信号确定要用于修改输入信号的补偿值。 光接收机可以使用补偿值来调整输入信号以形成修改的输入信号。 补偿值可用于修改输入信号的频率或相位。 光接收机可以基于经修改的输入信号来确定表示与输入信号相关联的估计相位的相位估计值。 光接收机可以组合补偿值和相位估计值以形成相位调整信号,可以组合输入信号和相位调整信号以形成输出信号,并且可以输出输出信号。

Patent Agency Ranking