公开(公告)号：US11502254B2

公开(公告)日：2022-11-15

申请号：US16147199

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Nathan Strutt ,  Albert Chen ,  Oleg Golonzka

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory device structure includes a first electrode, a second electrode, a switching layer between the first electrode and the second electrode, where the switching layer is to transition between first and second resistive states at a voltage threshold. The memory device further includes an oxygen exchange layer between the switching layer and the second electrode, where the oxygen exchange layer includes a metal and a sidewall oxide in contact with a sidewall of the oxygen exchange layer. The sidewall oxide includes the metal of the oxygen exchange layer and oxygen, and has a lateral thickness that exceed a thickness of the switching layer.

公开(公告)号：US20200343445A1

公开(公告)日：2020-10-29

申请号：US16396465

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Nathan Strutt ,  Albert Chen ,  Pedro Quintero ,  Oleg Golonzka

IPC: H01L45/00 ,  G11C13/00

Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.

公开(公告)号：US11621395B2

公开(公告)日：2023-04-04

申请号：US16396465

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Nathan Strutt ,  Albert Chen ,  Pedro Quintero ,  Oleg Golonzka

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.

公开(公告)号：US11462684B2

公开(公告)日：2022-10-04

申请号：US16226198

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Albert Chen ,  Nathan Strutt ,  Oleg Golonzka ,  Pedro Quintero ,  Christopher J. Jezewski ,  Elijah V. Karpov

IPC: H01L45/00

Abstract: An RRAM device is disclosed. The RRAM device includes a bottom electrode, a high-k material on the bottom electrode, a top electrode, a top contact on the top electrode and an encapsulating layer of Al2O3. The encapsulating layer encapsulates the bottom electrode, the high-k material, the top electrode and the top contact.