公开(公告)号：US20250105095A1

公开(公告)日：2025-03-27

申请号：US18471356

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Bozidar Marinkovic ,  Benjamin Kriegel ,  Payam Amin ,  Dolly Natalia Ruiz Amador ,  Thomas Jacroux ,  Makram Abd El Qader ,  Tofizur RAHMAN ,  Xiandong Yang ,  Conor P. Puls

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528

Abstract: An IC device may include one or more vias for delivering power to one or more transistors in the IC device. A via may have one or more widened ends to increase capacitance and decrease resistance. A transistor may include a source electrode over a source region and a drain electrode over a drain region. The source region or drain region may be in a support structure that has one or more semiconductor materials. The via has a body section and two end sections, the body section is between the end sections. One or both end sections are wider than the body section, e.g., by approximately 6 nanometers to approximately 12 nanometers. One end section is connected to an interconnect at the backside of the support structure. The other end section is connected to a jumper, which is connected to the source electrode or drain electrode.

公开(公告)号：US11990472B2

公开(公告)日：2024-05-21

申请号：US17030212

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Michael K. Harper ,  William Hsu ,  Biswajeet Guha ,  Tahir Ghani ,  Niels Zussblatt ,  Jeffrey Miles Tan ,  Benjamin Kriegel ,  Mohit K. Haran ,  Reken Patel ,  Oleg Golonzka ,  Mohammad Hasan

IPC: H01L27/088 ,  G11C5/06 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  G11C5/06 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.