公开(公告)号：US20230320057A1

公开(公告)日：2023-10-05

申请号：US17711875

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Leonard Guler ,  Mohit Haran ,  Smita Shridharan ,  Reken Patel ,  Charles Wallace ,  Chanaka Munasinghe ,  Pratik Patel

IPC: H01L27/11 ,  H01L27/02 ,  G11C11/412 ,  H01L21/768 ,  H01L23/522 ,  H01L29/423

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  G11C11/412 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/42392

Abstract: Integrated circuit (IC) devices include transistors with gate, source and drain contact metallization, some of which are jumpered together by a metallization that is recessed below a height of other metallization that is not jumpered. The jumper metallization may provide a local interconnect between terminals of one transistor or adjacent transistors, for example between a gate of one transistor and a source/drain of another transistor. The jumper metallization may not induce the same pitch constraints faced by interconnect line metallization levels employed for more general interconnection. In some examples, a static random-access memory (SRAM) bit-cell includes a jumper metallization joining two transistors of the cell to reduce cell height for a given feature patterning capability.

公开(公告)号：US20240404917A1

公开(公告)日：2024-12-05

申请号：US18204864

申请日：2023-06-01

Applicant: Intel Corporation

Inventor： Sikandar Abbas ,  Chanaka Munasinghe ,  Leonard Guler ,  Reza Bayati ,  Madeleine Stolt ,  Makram Abd El Qader ,  Pratik Patel ,  Anindya Dasgupta

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528

Abstract: Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.