公开(公告)号：US20220261949A1

公开(公告)日：2022-08-18

申请号：US17734983

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Chandra S. GURRAM ,  Gang Y. CHEN ,  Subramaniam MAIYURAN ,  Supratim PAL ,  Ashutosh GARG ,  Jorge E. PARRA ,  Darin M. STARKEY ,  Guei-Yuan LUEH ,  Wei-Yu CHEN

IPC: G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a software and hardware optimization that manages scenarios where a write operation to a register is less than an entirety of the register. A compiler detects instructions that make partial writes to the same register, groups such instructions, and provides hints to hardware of the partial write. The execution unit combines the output data for grouped instructions and updates the destination register as single write instead of multiple separate partial writes.

公开(公告)号：US20220308877A1

公开(公告)日：2022-09-29

申请号：US17213874

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Subramaniam MAIYURAN ,  Sudarshanram SHETTY ,  Travis SCHLUESSLER ,  Guei-Yuan LUEH ,  PingHang CHEUNG ,  Srividya KARUMURI ,  Chandra S. GURRAM ,  Shuai MU ,  Vikranth VEMULAPALLI

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0837

Abstract: A graphics processing apparatus includes a graphics processor and a constant cache. The graphics processor has a number of execution instances that will generate requests for constant data from the constant cache. The constant cache stores constants of multiple constant types. The constant cache has a single level of hierarchy to store the constant data. The constant cache has a banking structure based on the number of execution instances, where the execution instances generate requests for the constant data with unified messaging that is the same for the different types of constant data.

公开(公告)号：US20210192673A1

公开(公告)日：2021-06-24

申请号：US16726659

申请日：2019-12-24

Applicant: Intel Corporation

Inventor： Chandra S. GURRAM ,  Gang Y. CHEN ,  Subramaniam MAIYURAN ,  Supratim PAL ,  Ashutosh GARG ,  Jorge E. PARRA ,  Darin M. STARKEY ,  Guei-Yuan LUEH ,  Wei-Yu CHEN

IPC: G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a software and hardware optimization that manages scenarios where a write operation to a register is less than an entirety of the register. A compiler detects instructions that make partial writes to the same register, groups such instructions, and provides hints to hardware of the partial write. The execution unit combines the output data for grouped instructions and updates the destination register as single write instead of multiple separate partial writes.