公开(公告)号：US20220261949A1

公开(公告)日：2022-08-18

申请号：US17734983

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Chandra S. GURRAM ,  Gang Y. CHEN ,  Subramaniam MAIYURAN ,  Supratim PAL ,  Ashutosh GARG ,  Jorge E. PARRA ,  Darin M. STARKEY ,  Guei-Yuan LUEH ,  Wei-Yu CHEN

IPC: G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a software and hardware optimization that manages scenarios where a write operation to a register is less than an entirety of the register. A compiler detects instructions that make partial writes to the same register, groups such instructions, and provides hints to hardware of the partial write. The execution unit combines the output data for grouped instructions and updates the destination register as single write instead of multiple separate partial writes.

公开(公告)号：US20210192673A1

公开(公告)日：2021-06-24

申请号：US16726659

申请日：2019-12-24

Applicant: Intel Corporation

Inventor： Chandra S. GURRAM ,  Gang Y. CHEN ,  Subramaniam MAIYURAN ,  Supratim PAL ,  Ashutosh GARG ,  Jorge E. PARRA ,  Darin M. STARKEY ,  Guei-Yuan LUEH ,  Wei-Yu CHEN

IPC: G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a software and hardware optimization that manages scenarios where a write operation to a register is less than an entirety of the register. A compiler detects instructions that make partial writes to the same register, groups such instructions, and provides hints to hardware of the partial write. The execution unit combines the output data for grouped instructions and updates the destination register as single write instead of multiple separate partial writes.