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    Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits
    1.
    发明授权
    Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits 有权

    公开(公告)号：US12086080B2

    公开(公告)日：2024-09-10

    申请号：US17033728

    申请日：2020-09-26

    Applicant: Intel Corporation

    Inventor： George Chrysos ,  Bhargavi Narayanasetty ,  Jesus Corbal ,  Ching-Kai Liang ,  Chinmay Ashok ,  Francis Tseng

    IPC: G06F13/16 ,  G06F13/40

    CPC classification number: G06F13/1668 ,  G06F13/4027

    Abstract: Systems, methods, and apparatuses relating to a configurable accelerator having dataflow execution circuits are described. In one embodiment, a hardware accelerator includes a plurality of dataflow execution circuits that each comprise a register file, a plurality of execution circuits, and a graph station circuit comprising a plurality of dataflow operation entries that each include a respective ready field that indicates when an input operand for a dataflow operation is available in the register file, and the graph station circuit is to select for execution a first dataflow operation entry when its input operands are available, and clear ready fields of the input operands in the first dataflow operation entry when a result of the execution is stored in the register file; a cross dependence network coupled between the plurality of dataflow execution circuits to send data between the plurality of dataflow execution circuits according to a second dataflow operation entry; and a memory execution interface coupled between the plurality of dataflow execution circuits and a cache bank to send data between the plurality of dataflow execution circuits and the cache bank according to a third dataflow operation entry.

    Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator
    3.
    发明授权
    Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator 有权

    公开(公告)号：US10817291B2

    公开(公告)日：2020-10-27

    申请号：US16370915

    申请日：2019-03-30

    Applicant: Intel Corporation

    Inventor： Jesus Corbal ,  Rohan Sharma ,  Simon Steely, Jr. ,  Chinmay Ashok ,  Kent D. Glossop ,  Dennis Bradford ,  Paul Caprioli ,  Louise Huot ,  Kermin ChoFleming ,  Barry Tannenbaum

    IPC: G06F9/30 ,  G06F15/82

    Abstract: Systems, methods, and apparatuses relating to swizzle operations and disable operations in a configurable spatial accelerator (CSA) are described. Certain embodiments herein provide for an encoding system for a specific set of swizzle primitives across a plurality of packed data elements in a CSA. In one embodiment, a CSA includes a plurality of processing elements, a circuit switched interconnect network between the plurality of processing elements, and a configuration register within each processing element to store a configuration value having a first portion that, when set to a first value that indicates a first mode, causes the processing element to pass an input value to operation circuitry of the processing element without modifying the input value, and, when set to a second value that indicates a second mode, causes the processing element to perform a swizzle operation on the input value to form a swizzled input value before sending the swizzled input value to the operation circuitry of the processing element, and a second portion that causes the processing element to perform an operation indicated by the second portion the configuration value on the input value in the first mode and the swizzled input value in the second mode with the operation circuitry.

    Techniques to enable communication between a processor and voltage regulator
    5.
    发明授权
    Techniques to enable communication between a processor and voltage regulator 有权

    公开(公告)号：US10168758B2

    公开(公告)日：2019-01-01

    申请号：US15279744

    申请日：2016-09-29

    Applicant: Intel Corporation

    Inventor： Anupama Suryanarayanan ,  Avinash N. Ananthakrishnan ,  Chinmay Ashok ,  Jeremy J. Shrall

    IPC: G06F1/26 ,  G06F1/32 ,  G06F13/42

    Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.

    APPARATUSES, METHODS, AND SYSTEMS FOR SWIZZLE OPERATIONS IN A CONFIGURABLE SPATIAL ACCELERATOR
    8.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS FOR SWIZZLE OPERATIONS IN A CONFIGURABLE SPATIAL ACCELERATOR 审中-公开

    公开(公告)号：US20200310797A1

    公开(公告)日：2020-10-01

    申请号：US16370915

    申请日：2019-03-30

    Applicant: Intel Corporation

    Inventor： Jesus Corbal ,  Rohan Sharma ,  Simon Steely, JR. ,  Chinmay Ashok ,  Kent D. Glossop ,  Dennis Bradford ,  Paul Caprioli ,  Louise Huot ,  Kermin ChoFleming ,  Barry Tannenbaum

    IPC: G06F9/30 ,  G06F9/54

    Abstract: Systems, methods, and apparatuses relating to swizzle operations and disable operations in a configurable spatial accelerator (CSA) are described. Certain embodiments herein provide for an encoding system for a specific set of swizzle primitives across a plurality of packed data elements in a CSA. In one embodiment, a CSA includes a plurality of processing elements, a circuit switched interconnect network between the plurality of processing elements, and a configuration register within each processing element to store a configuration value having a first portion that, when set to a first value that indicates a first mode, causes the processing element to pass an input value to operation circuitry of the processing element without modifying the input value, and, when set to a second value that indicates a second mode, causes the processing element to perform a swizzle operation on the input value to form a swizzled input value before sending the swizzled input value to the operation circuitry of the processing element, and a second portion that causes the processing element to perform an operation indicated by the second portion the configuration value on the input value in the first mode and the swizzled input value in the second mode with the operation circuitry.

    Techniques for restricted deployment of targeted processor firmware updates
    10.
    发明授权
    Techniques for restricted deployment of targeted processor firmware updates 有权

    公开(公告)号：US12229269B2

    公开(公告)日：2025-02-18

    申请号：US17127122

    申请日：2020-12-18

    Applicant: Intel Corporation

    Inventor： Chinmay Ashok ,  Vasudevan Srinivasan ,  Atanas K. Iwanow ,  Martin G. Dixon ,  Scott J. Cape ,  Scott Bobholz ,  David T. Mayo ,  Vinila Rose ,  Lorie Wigle ,  Jason Kennedy

    IPC: G06F21/57 ,  G06F21/10 ,  G06F21/44

    Abstract: Methods and apparatus for restricted deployment of targeted processor firmware updates. During a patch enabling per-work flow, service entitlement license information comprising one of more service entitlements is generated and provisioned on one or more computing platforms. A restricted deployment microcode (uCode) update release (aka uCode patch) targeted for platforms having CPUs and/or XPUs with certain part identifier is sent to the one or more platforms. Run-time software and/or firmware on the platforms are executed to access the provisioned service entitlement license information, which is used to authentic and verify the restricted deployment uCode update release using a service entitlement having a part identifier associated with the platform's CPU. In one solution, authentication is performed using a hash-matching scheme and verification is used to verify the platform is properly licensed to load uCode included in the restricted deployment microcode (uCode) update release into the CPU.

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