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1.
公开(公告)号:US20230422639A1
公开(公告)日:2023-12-28
申请号:US17850746
申请日:2022-06-27
Applicant: Intel Corporation
Inventor: Shafaat Ahmed , Gowtham Sriram Jawaharram , Cyrus M. Fox , Jose L. Cruz-Campa , Kriti Agarwal , Jian Jiao , Hong Li , Bharat V. Krishnan , Ervin T. Hill, III
IPC: H01L45/00 , H01L23/528
CPC classification number: H01L45/06 , H01L23/5283 , H01L45/1233 , H01L45/1253
Abstract: A semiconductor structure, system and method. The semiconductor structure comprises: a substrate including circuitry therein; and a semiconductor stack on the substrate, the semiconductor stack including: a first electrically conductive layer including a metal and electrically coupled to the circuitry of the substrate; and a second electrically conductive layer between the substrate and the first electrically conductive layer, the second electrically conductive layer including one of a refractory metal, or a combination including silicon, carbon and nitride. The second electrically conductive layer may serve as a barrier layer between the first electrically conductive layer and the material of the underlying substrate, in this manner avoiding the formation of an intermixing region between the metal of the first electrically conductive layer and the material of the substrate during deposition of the metal.
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公开(公告)号:US20230209834A1
公开(公告)日:2023-06-29
申请号:US17561385
申请日:2021-12-23
Applicant: Intel Corporation
Inventor: Shafaat Ahmed , Cyrus M. Fox , Gregory C. Herdt , Gowtham Sriram Jawaharram , Viswas Reddy Pola
IPC: H01L27/11597 , H01L27/11514
CPC classification number: H01L27/11597 , H01L27/11514
Abstract: A memory device comprising a three dimensional crosspoint memory array comprising a plurality of memory cells, wherein a memory cell is coupled between a first access line and a second access line and comprises an electrode coupled to a storage element, wherein the electrode comprises silicon carbide (SixCy).
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3.
公开(公告)号:US20230354723A1
公开(公告)日:2023-11-02
申请号:US17735113
申请日:2022-05-02
Applicant: Intel Corporation
Inventor: Gowtham Sriram Jawaharram , Cyrus M. Fox , Jose L. Cruz-Campa , Shafaat Ahmed , Qiaoer Zhou , Duo Li , Hong Li
CPC classification number: H01L45/1253 , H01L27/2427 , H01L27/2481 , H01L45/06 , H01L45/1675
Abstract: In one embodiment, a crosspoint memory device is manufactured by forming a material stack and patterning the material stack to form a plurality of memory cells of the cross point memory device. Forming the material stack includes depositing a select device (SD) region material comprising chalcogenide, depositing a layer comprising carbon on the SD region material at a temperature below 40° C., depositing an ohmic contact layer on the layer comprising carbon, and depositing a phase change material (PM) region material comprising chalcogenide on the ohmic contact layer.
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