公开(公告)号：US20230209834A1

公开(公告)日：2023-06-29

申请号：US17561385

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Shafaat Ahmed ,  Cyrus M. Fox ,  Gregory C. Herdt ,  Gowtham Sriram Jawaharram ,  Viswas Reddy Pola

IPC: H01L27/11597 ,  H01L27/11514

CPC classification number: H01L27/11597 ,  H01L27/11514

Abstract: A memory device comprising a three dimensional crosspoint memory array comprising a plurality of memory cells, wherein a memory cell is coupled between a first access line and a second access line and comprises an electrode coupled to a storage element, wherein the electrode comprises silicon carbide (SixCy).

公开(公告)号：US20230422639A1

公开(公告)日：2023-12-28

申请号：US17850746

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Shafaat Ahmed ,  Gowtham Sriram Jawaharram ,  Cyrus M. Fox ,  Jose L. Cruz-Campa ,  Kriti Agarwal ,  Jian Jiao ,  Hong Li ,  Bharat V. Krishnan ,  Ervin T. Hill, III

IPC: H01L45/00 ,  H01L23/528

CPC classification number: H01L45/06 ,  H01L23/5283 ,  H01L45/1233 ,  H01L45/1253

Abstract: A semiconductor structure, system and method. The semiconductor structure comprises: a substrate including circuitry therein; and a semiconductor stack on the substrate, the semiconductor stack including: a first electrically conductive layer including a metal and electrically coupled to the circuitry of the substrate; and a second electrically conductive layer between the substrate and the first electrically conductive layer, the second electrically conductive layer including one of a refractory metal, or a combination including silicon, carbon and nitride. The second electrically conductive layer may serve as a barrier layer between the first electrically conductive layer and the material of the underlying substrate, in this manner avoiding the formation of an intermixing region between the metal of the first electrically conductive layer and the material of the substrate during deposition of the metal.

公开(公告)号：US20230354723A1

公开(公告)日：2023-11-02

申请号：US17735113

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Gowtham Sriram Jawaharram ,  Cyrus M. Fox ,  Jose L. Cruz-Campa ,  Shafaat Ahmed ,  Qiaoer Zhou ,  Duo Li ,  Hong Li

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1675

Abstract: In one embodiment, a crosspoint memory device is manufactured by forming a material stack and patterning the material stack to form a plurality of memory cells of the cross point memory device. Forming the material stack includes depositing a select device (SD) region material comprising chalcogenide, depositing a layer comprising carbon on the SD region material at a temperature below 40° C., depositing an ohmic contact layer on the layer comprising carbon, and depositing a phase change material (PM) region material comprising chalcogenide on the ohmic contact layer.

公开(公告)号：US20230276639A1

公开(公告)日：2023-08-31

申请号：US17682907

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Viswas Reddy Pola ,  Shafaat Ahmed ,  Gowtham Sriram Jawaharram ,  Gregory C. Herdt

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1675

Abstract: A memory device comprising a memory array comprising a plurality of memory cells and a metal silicide layer, wherein a memory cell is coupled between a first access line and a second access line and comprises an electrode coupling a storage element to the first access line, wherein the metal silicide layer is between the electrode and the first access line.

公开(公告)号：US20240105588A1

公开(公告)日：2024-03-28

申请号：US17935999

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Ilya V. Karpov ,  Shafaat Ahmed ,  Matthew V. Metz ,  Darren Anthony Denardis ,  Nafees Aminul Kabir ,  Tristan A. Tronic

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53223

Abstract: An IC device includes a multilayer metal line that is at least partially surrounded by one or more electrical insulators. The multilayer metal line may be formed by stacking four layers on top of one another. The four layers may include a first layer between a second layer and a third layer. The first layer may include Al. The second or third layer may include W. The fourth layer may be a conductive or dielectric layer. The second layer, third layer, and fourth layer can protect the first layer from defects in Al core layer during fabrication or operation of the multilayer metal line. Substrative etch may be performed on the stack of the four layers to form openings. An electrical insulator may be deposited into to the openings to form multiple metal lines that are separated by the electrical insulator. A via may be formed over the third layer.

公开(公告)号：US20230157035A1

公开(公告)日：2023-05-18

申请号：US17528733

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Shafaat Ahmed ,  Viswas Reddy Pola ,  Gregory C. Herdt

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L45/1675 ,  H01L25/18

Abstract: An apparatus comprising a substrate; and an interconnect comprising a first metal layer between and in contact with a second metal layer and a third metal layer, wherein the first metal layer has a resistivity that is lower than a resistivity of the second metal layer and a resistivity of the third metal layer.