公开(公告)号：US20180004659A1

公开(公告)日：2018-01-04

申请号：US15201366

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Daniel GREENSPAN

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F12/0868 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/604 ,  Y02D10/13

Abstract: A memory subsystem includes a flag to indicate high compressibility, which enables a cache controller to selectively avoid access to the data from a memory resource based on an indication of the flag. The main memory device stores data and the auxiliary memory device stores a copy of the data. The cache controller can determine whether the memory location includes highly compressible data and store a flag locally at the cache controller as a representation for high compressibility. The flag is accessible without external input/output (I/O) from the cache controller, and indicates whether the data includes highly compressible data. The flag can optionally indicate a type of highly compressible data. In response to a memory access request for the memory location, the cache controller can return fulfillment of the memory access request according to the representation of high compressibility indicated by the flag.

公开(公告)号：US20160299869A1

公开(公告)日：2016-10-13

申请号：US15032488

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Daniel GREENSPAN

IPC: G06F13/42 ,  G06F13/36

CPC classification number: G06F13/42 ,  G06F13/36 ,  G06F13/4243 ,  G06F2213/0038

Abstract: A method of transition minimized low speed data transfer is described herein. In an embodiment, a data rate of a set data to be transmitted on a data bus is determined. A one hot value is encoded on the data bus in response to a low data rate. An XOR operation is performed with a previous state of the data bus and the encoded one hot value. Additionally, a resulting value of the XOR operation is driven onto the data bus.

Abstract translation: 本文描述了一种转换的最小化的低速数据传送方法。 在一个实施例中，确定要在数据总线上发送的设定数据的数据速率。 响应于低数据速率，在数据总线上编码一个热值。 使用数据总线的先前状态和编码的一个热值来执行XOR操作。 此外，XOR运算的结果值被驱动到数据总线上。

公开(公告)号：US20190108138A1

公开(公告)日：2019-04-11

申请号：US16105434

申请日：2018-08-20

Applicant: Intel Corporation

Inventor： Daniel GREENSPAN ,  Blaise FANNING ,  Yoav LOSSIN ,  Asaf RUBINSTEIN

IPC: G06F12/123 ,  G06F12/0891 ,  G06F12/0897

Abstract: A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy.

公开(公告)号：US20170177482A1

公开(公告)日：2017-06-22

申请号：US14975487

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Daniel GREENSPAN

IPC: G06F12/08 ,  G06F9/44 ,  G06F3/06

CPC classification number: G06F12/0815 ,  G06F3/0602 ,  G06F3/0659 ,  G06F3/0685 ,  G06F9/4406 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/60 ,  G06F2212/621

Abstract: An apparatus is described that includes a memory controller to interface to a multi-level system memory having a higher level and a lower level. The memory controller includes register space to indicate first and second modes of operation. In the first mode of operation the higher level is available and the lower level is unavailable. In the second mode of operation the higher level is available and the lower level is available.