公开(公告)号：US20150379666A1

公开(公告)日：2015-12-31

申请号：US14317234

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Dmitar Redzic ,  Aleksandar Beric ,  Edwin Van Dalen

IPC: G06T1/20 ,  G06T3/40 ,  G06T3/00

CPC classification number: G06T1/20 ,  G06T3/0093 ,  G06T3/4007 ,  G06T2200/28

Abstract: Technologies are presented that allow efficient pixel-based image and/or video warping and scaling. An image processing system may include a memory and an accelerator unit communicatively coupled with the memory. The accelerator unit may, based on configuration settings, receive, from a memory, at least a portion of an input image as an array of neighboring four-cornered shapes; and process each shape by: determining locations of an array of output pixels delineated by four corner locations of the shape via linearization; interpolating a value of each pixel of the array of output pixels; and storing the interpolated pixel values in the memory. For warping, the array of neighboring four-cornered shapes may include an array of neighboring distorted tetragons that approximate distortion of the input image, and the interpolated pixel values may represent a warped output image. For scaling, the array of neighboring four-cornered shapes may include an array of neighboring rectangles.

Abstract translation: 提出了允许有效的基于像素的图像和/或视频翘曲和缩放的技术。 图像处理系统可以包括与存储器通信地耦合的存储器和加速器单元。 加速器单元可以基于配置设置从存储器接收输入图像的至少一部分作为相邻四角形状的阵列; 并且通过以下方式处理每个形状：通过线性化来确定由形状的四个角位置描绘的输出像素的阵列的位置; 内插输出像素阵列的每个像素的值; 以及将内插的像素值存储在存储器中。 对于翘曲，相邻的四角形状的阵列可以包括近似失真的四边形的阵列，其近似输入图像的失真，并且内插的像素值可以表示翘曲的输出图像。 对于缩放，相邻四角形状的阵列可以包括相邻矩形的阵列。

公开(公告)号：US09443281B2

公开(公告)日：2016-09-13

申请号：US14317234

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Dmitar Redzic ,  Aleksandar Beric ,  Edwin Van Dalen

IPC: G06T1/20 ,  G06T3/40 ,  G06T3/00

CPC classification number: G06T1/20 ,  G06T3/0093 ,  G06T3/4007 ,  G06T2200/28

Abstract: Technologies are presented that allow efficient pixel-based image and/or video warping and scaling. An image processing system may include a memory and an accelerator unit communicatively coupled with the memory. The accelerator unit may, based on configuration settings, receive, from a memory, at least a portion of an input image as an array of neighboring four-cornered shapes; and process each shape by: determining locations of an array of output pixels delineated by four corner locations of the shape via linearization; interpolating a value of each pixel of the array of output pixels; and storing the interpolated pixel values in the memory. For warping, the array of neighboring four-cornered shapes may include an array of neighboring distorted tetragons that approximate distortion of the input image, and the interpolated pixel values may represent a warped output image. For scaling, the array of neighboring four-cornered shapes may include an array of neighboring rectangles.

Abstract translation: 提出了允许有效的基于像素的图像和/或视频翘曲和缩放的技术。 图像处理系统可以包括与存储器通信地耦合的存储器和加速器单元。 加速器单元可以基于配置设置从存储器接收输入图像的至少一部分作为相邻四角形状的阵列; 并且通过以下方式处理每个形状：通过线性化来确定由形状的四个角位置描绘的输出像素的阵列的位置; 内插输出像素阵列的每个像素的值; 以及将内插的像素值存储在存储器中。 对于翘曲，相邻的四角形状的阵列可以包括近似失真的四边形的阵列，其近似输入图像的失真，并且内插的像素值可以表示翘曲的输出图像。 对于缩放，相邻四角形状的阵列可以包括相邻矩形的阵列。