公开(公告)号：US20210073129A1

公开(公告)日：2021-03-11

申请号：US17086243

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Rahul R. SHAH ,  Omkar MASLEKAR ,  Priya AUTEE ,  Edwin VERPLANKE ,  Andrew J. HERDRICH ,  Jeffrey D. CHAMBERLAIN

IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/1009 ,  G06F9/30

Abstract: Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.

公开(公告)号：US20190340123A1

公开(公告)日：2019-11-07

申请号：US16514226

申请日：2019-07-17

Applicant: Intel Corporation

Inventor： Andrew J. HERDRICH ,  Priya AUTEE ,  Abhishek KHADE ,  Patrick LU ,  Edwin VERPLANKE ,  Vivekananthan SANJEEPAN

IPC: G06F12/0802

Abstract: Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is successful or not successful. If a request is not successful, the controller can provide feedback indicating one or more aspects of the request that are not permitted. The application, software, or hardware can submit another request, a modified request, based on the feedback to attempt to lock a portion of the cache or TLB.

公开(公告)号：US20230325241A1

公开(公告)日：2023-10-12

申请号：US18043259

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Andrew J. HERDRICH ,  Yen-Cheng LIU ,  Venkateswara MADDURI ,  Krishnakumar K. GANAPATHY ,  Edwin VERPLANKE ,  Christopher GIANOS ,  Hanna ALAM ,  Joseph NUZMAN ,  Larisa NOVAKOVSKY

IPC: G06F9/50

CPC classification number: G06F9/5016 ,  G06F2209/504

Abstract: Embodiments for allocating shared resources are disclosed. In an embodiment, an apparatus includes a core and a hardware rate selector. The hardware rate selector is to, in response to a first indication that demand for memory bandwidth from the core has reached a threshold value, determine a delay value to be used to limit allocation of memory bandwidth to the core. The hardware rate selector includes a controller having a first counter to count a second indication of demand for memory bandwidth from the first core and a second counter to count expirations of time windows. The first indication is based on a difference between the first counter value and the second counter value.

公开(公告)号：US20230082780A1

公开(公告)日：2023-03-16

申请号：US17471889

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Chenmin SUN ,  Yipeng WANG ,  Rahul R. SHAH ,  Ren WANG ,  Sameh GOBRIEL ,  Hongjun NI ,  Mrittika GANGULI ,  Edwin VERPLANKE

IPC: G06F9/50

Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.

公开(公告)号：US20220155847A1

公开(公告)日：2022-05-19

申请号：US17559170

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Konstantin ANANYEV ,  Anatoly BURAKOV ,  David HUNT ,  Chris MACNAMARA ,  Edwin VERPLANKE ,  Omkar MASLEKAR ,  Gilbert NEIGER ,  Rajesh M. SANKARAN

IPC: G06F1/3296 ,  G06F3/06

Abstract: Examples described herein relate to circuitry to cause a processor to enter reduced power consumption state and circuitry to, based on a write to one or more of multiple memory regions, cause the processor to exit reduced power consumption state, wherein the multiple memory regions store receive descriptors associated with one or more packets received by a network interface device. In some examples, multiple memory regions are defined by a driver of the network interface device. In some examples, the reduced power consumption state comprises a TPAUSE state.

公开(公告)号：US20220103530A1

公开(公告)日：2022-03-31

申请号：US17544699

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Daniel DALY ,  Anjali Singhai JAIN ,  Yadong LI ,  Stephen DOYLE ,  Naru Dames SUNDAR ,  Chih-Jen CHANG ,  Sailesh BISSESSUR ,  Andrew CUNNINGHAM ,  Edwin VERPLANKE ,  Patrick FLEMING

IPC: H04L9/08

Abstract: Examples described herein relate to a network interface device that includes circuitry, configured to perform encryption of data, generate one or more packets from the encrypted data, cause transmission of the one or more packets with the encrypted data, manage reliability of transport of the transmitted one or more packets with the encrypted data, and share protocol state information between a host system and the network interface device using connectivity based on user space accessible queues.

公开(公告)号：US20210042146A1

公开(公告)日：2021-02-11

申请号：US17077796

申请日：2020-10-22

Applicant: Intel Corporation

Inventor： Matthew FLEMING ,  Edwin VERPLANKE ,  Andrew HERDRICH ,  Ravishankar IYER

IPC: G06F9/46 ,  G06F9/455 ,  G06F11/30

Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.

公开(公告)号：US20200012514A1

公开(公告)日：2020-01-09

申请号：US16408159

申请日：2019-05-09

Applicant: Intel Corporation

Inventor： Matthew FLEMING ,  Edwin VERPLANKE ,  Andrew HERDRICH ,  Ravishankar IYER

IPC: G06F9/46 ,  G06F9/455

Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.

公开(公告)号：US20240160568A1

公开(公告)日：2024-05-16

申请号：US17987773

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Kapil SOOD ,  Lokpraveen MOSUR ,  Aneesh AGGARWAL ,  Niall D. MCDONNELL ,  Chitra NATARAJAN ,  Ritu GUPTA ,  Edwin VERPLANKE ,  George Leonard TKACHUK

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Examples include techniques associated with data movement to a cache in a disaggregated die system. Examples include circuitry at a first die receiving and granting requests to move data to a first cache resident on the first die or to a second cache resident on a second die that also includes a core of a processor. The granting of the request based, at least in part, on a traffic source type associated with a source of the request.

公开(公告)号：US20220114270A1

公开(公告)日：2022-04-14

申请号：US17560193

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Ren WANG ,  Sameh GOBRIEL ,  Somnath PAUL ,  Yipeng WANG ,  Priya AUTEE ,  Abhirupa LAYEK ,  Shaman NARAYANA ,  Edwin VERPLANKE ,  Mrittika GANGULI ,  Jr-Shian TSAI ,  Anton SOROKIN ,  Suvadeep BANERJEE ,  Abhijit DAVARE ,  Desmond KIRKPATRICK

IPC: G06F21/62

Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.