公开(公告)号：US20250076954A1

公开(公告)日：2025-03-06

申请号：US18883276

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Vivek GARG ,  Ankush VARMA ,  Krishnakanth SISTLA ,  Nikhil GUPTA ,  Nikethan Shivanand BALIGAR ,  Stephen WANG ,  Nilanjan PALIT ,  Timothy Yee-Kwong KAM ,  Adwait PURANDARE ,  Ujjwal GUPTA ,  Stanley CHEN ,  Dorit SHAPIRA ,  Shruthi VENUGOPAL ,  Suresh CHEMUDUPATI ,  Rupal PARIKH ,  Eric DEHAEMER ,  Pavithra SAMPATH ,  Phani Kumar KANDULA ,  Yogesh BANSAL ,  Dean MULLA ,  Michael TULANOWSKI ,  Stephen Paul HAAKE ,  Andrew HERDRICH ,  Ripan DAS ,  Nazar Syed HAIDER ,  Aman SEWANI

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US20210374848A1

公开(公告)日：2021-12-02

申请号：US17401575

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Andrew HERDRICH ,  Edwin VERPLANKE ,  Ravishankar IYER ,  Christopher GIANOS ,  Jeffrey D. CHAMBERLAIN ,  Ronak SINGH ,  Julius MANDELBLAT ,  Bret Toll

IPC: G06Q40/02 ,  G06F12/0875 ,  G06F12/0897

Abstract: Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.

公开(公告)号：US20180278493A1

公开(公告)日：2018-09-27

申请号：US15470664

申请日：2017-03-27

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Thomas WILLHALM ,  Andrew HERDRICH ,  Edwin VERPLANKE

IPC: H04L12/24 ,  H04L12/947 ,  H04L5/00 ,  H04L12/911

CPC classification number: H04L41/5019 ,  H04L5/0055 ,  H04L41/0896 ,  H04L41/5003 ,  H04L47/783 ,  H04L49/25

Abstract: Examples include techniques to meet quality of service (QoS) requirements for a fabric point to point connection. Examples include an application hosted by a compute node coupled with a fabric requesting bandwidth for a point to point connection through the fabric and the request being granted or not granted based at least partially on whether bandwidth is available for allocation to meet one or more QoS requirements.

公开(公告)号：US20210042146A1

公开(公告)日：2021-02-11

申请号：US17077796

申请日：2020-10-22

Applicant: Intel Corporation

Inventor： Matthew FLEMING ,  Edwin VERPLANKE ,  Andrew HERDRICH ,  Ravishankar IYER

IPC: G06F9/46 ,  G06F9/455 ,  G06F11/30

Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.

公开(公告)号：US20200012514A1

公开(公告)日：2020-01-09

申请号：US16408159

申请日：2019-05-09

Applicant: Intel Corporation

Inventor： Matthew FLEMING ,  Edwin VERPLANKE ,  Andrew HERDRICH ,  Ravishankar IYER

IPC: G06F9/46 ,  G06F9/455

Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.