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公开(公告)号：US20190004583A1
公开(公告)日：2019-01-03
申请号：US15638573
申请日：2017-06-30
Applicant: Intel Corporation
Inventor： Yiftach Gilad , Ariel Szapiro , Elkana Korem , Alexander Gendler
Abstract: Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.
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公开(公告)号：US10936041B2
公开(公告)日：2021-03-02
申请号：US16369793
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/32 , G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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公开(公告)号：US10809790B2
公开(公告)日：2020-10-20
申请号：US15638573
申请日：2017-06-30
Applicant: Intel Corporation
Inventor： Yiftach Gilad , Ariel Szapiro , Elkana Korem , Alexander Gendler
IPC: G06F1/32 , G06F1/324 , G06F1/08 , G06F1/3296 , H03K5/133 , H03K19/003 , G11C29/02 , G11C7/22 , G11C5/14 , H03K5/00
Abstract: Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.
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公开(公告)号：US11543878B2
公开(公告)日：2023-01-03
申请号：US17042804
申请日：2018-05-01
Applicant: Intel Corporation
Inventor： Efraim Rotem , Eliezer Weissmann , Eric Dehaemer , Alexander Gendler , Nadav Shulman , Krishnakanth Sistla , Nir Rosenzweig , Ankush Varma , Ariel Szapiro , Arye Albahari , Ido Melamed , Nir Misgav , Vivek Garg , Nimrod Angel , Adwait Purandare , Elkana Korem
IPC: G06F1/32 , G06F9/4401 , G06F1/329 , G06F1/3206 , G06F9/30 , G06F9/48
Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.
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Patent Agency Ranking
公开(公告)号：US20210271305A1
公开(公告)日：2021-09-02
申请号：US17183518
申请日：2021-02-24
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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公开(公告)号：US11385704B2
公开(公告)日：2022-07-12
申请号：US17183518
申请日：2021-02-24
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/32 , G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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公开(公告)号：US10921872B2
公开(公告)日：2021-02-16
申请号：US16369136
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Elkana Korem , Hanan Shomroni , Nadav Shulman
IPC: G06F1/324 , G06F1/3287 , G06F1/3234 , G06F1/3293 , G06F1/329
Abstract: In an embodiment, a processor includes processing engines to execute instructions and power limit logic. The power limit logic is to: in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine; determine a ratio of the soft throttling events to the hard throttling events; compare the determined ratio to a desired goal; and adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal. Other embodiments are described and claimed.
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公开(公告)号：US20200310511A1
公开(公告)日：2020-10-01
申请号：US16369793
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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公开(公告)号：US20200310509A1
公开(公告)日：2020-10-01
申请号：US16369136
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Elkana Korem , Hanan Shomroni , Nadav Shulman
IPC: G06F1/324 , G06F1/3234 , G06F1/3287 , G06F1/329 , G06F1/3293
Abstract: In an embodiment, a processor includes processing engines to execute instructions and power limit logic. The power limit logic is to: in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine; determine a ratio of the soft throttling events to the hard throttling events; compare the determined ratio to a desired goal; and adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal. Other embodiments are described and claimed.
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