公开(公告)号：US09971603B2

公开(公告)日：2018-05-15

申请号：US15438679

申请日：2017-02-21

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Peggy J. Irelan ,  Ofer Levy ,  Emile Ziedan ,  Grant G. Zhou

IPC: G06F9/38 ,  G06F11/34

CPC classification number: G06F9/3861 ,  G06F9/3857 ,  G06F11/3466 ,  G06F11/3476 ,  G06F2201/86 ,  G06F2201/88

Abstract: Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.