公开(公告)号：US20230169032A1

公开(公告)日：2023-06-01

申请号：US18102568

申请日：2023-01-27

Applicant: Intel Corporation

Inventor： NEVINE NASSIF ,  YEN-CHENG LIU ,  KRISHNAKANTH V. SISTLA ,  GERALD PASDAST ,  SIVA SOUMYA EACHEMPATI ,  TEJPAL SINGH ,  ANKUSH VARMA ,  MAHESH K. KUMASHIKAR ,  SRIKANTH NIMMAGADDA ,  CARLETON L. MOLNAR ,  VEDARAMAN GEETHA ,  JEFFREY D. CHAMBERLAIN ,  WILLIAM R. HALLECK ,  GEORGE Z. CHRYSOS ,  JOHN R. AYERS ,  DHEERAJ R. SUBBAREDDY

IPC: G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

CPC classification number: G06F15/7889 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/3869 ,  G06F9/5038 ,  G06F15/17312

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20160328335A1

公开(公告)日：2016-11-10

申请号：US14703420

申请日：2015-05-04

Applicant: Intel Corporation

Inventor： BINATA BHATTACHARYYA ,  AMY L. SANTONI ,  RAGHUNANDAN MAKARAM ,  FRANCIS X. MCKEEN ,  SIMON P. JOHNSON ,  GEORGE Z. CHRYSOS ,  SIDDHARTHA CHHABRA

IPC: G06F12/14 ,  H04L9/08

CPC classification number: H04L9/3242 ,  H04L9/0637 ,  H04L2209/12

Abstract: Systems and methods for memory protection for implementing trusted execution environment. An example processing system comprises: an on-package memory; a memory encryption engine (MEE) comprising a MEE cache, the MEE to: responsive to failing to locate, within the MEE cache, an encryption metadata associated with a data item loaded from an external memory, retrieve at least part of the encryption metadata from the OPM, and validate the data item using the encryption metadata.

Abstract translation: 用于实现可信执行环境的内存保护的系统和方法。 一个示例性处理系统包括：一个包装内存储器; 包括MEE缓存的存储器加密引擎（MEE），所述MEE响应于在所述MEE缓存内未能定位与从外部存储器加载的数据项相关联的加密元数据，从所述MEE缓存中检索至少部分所述加密元数据 OPM，并使用加密元数据验证数据项。

公开(公告)号：US20200334196A1

公开(公告)日：2020-10-22

申请号：US16917888

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： NEVINE NASSIF ,  YEN-CHENG LIU ,  KRISHNAKANTH V. SISTLA ,  GERALD PASDAST ,  SIVA SOUMYA EACHEMPATI ,  TEJPAL SINGH ,  ANKUSH VARMA ,  MAHESH K. KUMASHIKAR ,  SRIKANTH NIMMAGADDA ,  CARLETON L. MOLNAR ,  VEDARAMAN GEETHA ,  JEFFREY D. CHAMBERLAIN ,  WILLIAM R. HALLECK ,  GEORGE Z. CHRYSOS ,  JOHN R. AYERS ,  DHEERAJ R. SUBBAREDDY

IPC: G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20180173628A1

公开(公告)日：2018-06-21

申请号：US15835384

申请日：2017-12-07

Applicant: Intel Corporation

Inventor： CHUNHUI ZHANG ,  GEORGE Z. CHRYSOS ,  EDWARD T. GROCHOWSKI ,  RAMACHARAN SUNDARARAMAN ,  CHUNG-LUN CHAN ,  FEDERICO ARDANAZ

IPC: G06F12/0842 ,  G06F12/0817 ,  G06F9/38 ,  G06F12/0831

CPC classification number: G06F12/0842 ,  G06F9/38 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0835 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/621

Abstract: Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.