公开(公告)号：US20200349312A1

公开(公告)日：2020-11-05

申请号：US16854788

申请日：2020-04-21

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Alexander Gendler ,  Larisa Novakovsky ,  Anwar Azaarura Zaa'Rura ,  Afik Sela ,  Genadi Kazakevich ,  Alexandra Shainshein ,  Ariel Sabba

IPC: G06F30/3323 ,  G01R31/317 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36

Abstract: An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.