公开(公告)号：US20180188966A1

公开(公告)日：2018-07-05

申请号：US15393935

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Ashok Raj ,  Hemalatha Gurumoorthy ,  Ronald N. Story

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1666 ,  G06F11/2056 ,  G06F11/2094

Abstract: A systems and methods for dynamic address based minoring are disclosed. A system may include a processor, comprising a mirror address range register to store data indicating a location and a size of a first portion of a system memory to be mirrored. The processor may further include a memory controller coupled to the mirror address range register and including circuitry to cause a second portion of the system memory to mirror the first portion of the system memory.

公开(公告)号：US10387072B2

公开(公告)日：2019-08-20

申请号：US15393935

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Ashok Raj ,  Hemalatha Gurumoorthy ,  Ronald N. Story

IPC: G06F3/06 ,  G06F11/16 ,  G06F11/20

Abstract: A systems and methods for dynamic address based minoring are disclosed. A system may include a processor, comprising a mirror address range register to store data indicating a location and a size of a first portion of a system memory to be mirrored. The processor may further include a memory controller coupled to the mirror address range register and including circuitry to cause a second portion of the system memory to mirror the first portion of the system memory.