公开(公告)号：US09311241B2

公开(公告)日：2016-04-12

申请号：US13730957

申请日：2012-12-29

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Robert Chappell ,  Zhongying Zhang ,  Jason Bessette

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F2212/507

Abstract: A method is described that includes performing the following for a transactional operation in response to a request from a processing unit that is directed to a cache identifying a cache line. Reading the cache line, and, if the cache line is in a Modified cache coherency protocol state, forwarding the cache line to circuitry that will cause the cache line to be written to deeper storage, and, changing another instance of the cache line that is available to the processing unit for the transactional operation to an Exclusive cache coherency state.

Abstract translation: 描述了一种方法，其包括响应于来自处理单元的针对指定到高速缓存行的高速缓存的请求执行事务操作的以下操作。 读取高速缓存行，并且如果高速缓存行处于修改的高速缓存一致性协议状态，则将高速缓存行转发到将使高速缓存行被写入更深的存储的电路，并且改变高速缓存行的另一个实例 可用于处理单元的事务操作到独占高速缓存一致性状态。