公开(公告)号：US10248524B2

公开(公告)日：2019-04-02

申请号：US14998055

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F11/28 ,  G06F9/46 ,  G06F9/30 ,  G06F12/0811 ,  G06F9/38 ,  G11C7/10 ,  G06F11/22 ,  G06F11/263 ,  G06F12/0897 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F11/14 ,  G06F11/25

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US10210065B2

公开(公告)日：2019-02-19

申请号：US14757980

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F11/28 ,  G06F9/46 ,  G06F9/30 ,  G06F12/0811 ,  G06F9/38 ,  G11C7/10 ,  G06F11/22 ,  G06F11/263 ,  G06F12/0897 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F11/14 ,  G06F11/25

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US09535744B2

公开(公告)日：2017-01-03

申请号：US13931860

申请日：2013-06-29

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Matthew C. Merten ,  Christine E. Wang ,  Vijaykumar B. Kadgi ,  Rajesh S. Parthasarathy

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/467 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/466 ,  G06F9/528

Abstract: A processor, system, and method are described for continued retirement of operations during a commit of a speculative region of program code. For example, one embodiment of a method comprises the operations of identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and retiring one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete.

Abstract translation: 描述了处理器，系统和方法，用于在提交程序代码的推测区域期间继续退出操作。 例如，方法的一个实施例包括在程序代码中识别多个事务存储区域的操作，包括第一事务存储器区域; 以及即使当与第一事务存储器区域相关联的提交操作等待完成时，退出遵循第一事务存储器区域的多个操作中的一个或多个操作。

公开(公告)号：US20160202979A1

公开(公告)日：2016-07-14

申请号：US14757919

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F11/28 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/466 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/2236 ,  G06F11/25 ,  G06F11/263 ,  G06F12/0811 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/20 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/608 ,  G06F2212/621 ,  G11C7/1072

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Abstract translation: 公开了新的指令，逻辑，方法和装置来测试事务执行状态。 实施例包括解码第一指令以启动事务区域。 响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。 然后解码用于检测事务区域的事务执行的第二指令。 执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。 然后响应于第二指令，更新第一标志。 在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

公开(公告)号：US20160188479A1

公开(公告)日：2016-06-30

申请号：US14977659

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew Merten ,  Martin G. Dixon

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F11/28 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/466 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/2236 ,  G06F11/25 ,  G06F11/263 ,  G06F12/0811 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/20 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/608 ,  G06F2212/621 ,  G11C7/1072

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US09311241B2

公开(公告)日：2016-04-12

申请号：US13730957

申请日：2012-12-29

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Robert Chappell ,  Zhongying Zhang ,  Jason Bessette

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F2212/507

Abstract: A method is described that includes performing the following for a transactional operation in response to a request from a processing unit that is directed to a cache identifying a cache line. Reading the cache line, and, if the cache line is in a Modified cache coherency protocol state, forwarding the cache line to circuitry that will cause the cache line to be written to deeper storage, and, changing another instance of the cache line that is available to the processing unit for the transactional operation to an Exclusive cache coherency state.

Abstract translation: 描述了一种方法，其包括响应于来自处理单元的针对指定到高速缓存行的高速缓存的请求执行事务操作的以下操作。 读取高速缓存行，并且如果高速缓存行处于修改的高速缓存一致性协议状态，则将高速缓存行转发到将使高速缓存行被写入更深的存储的电路，并且改变高速缓存行的另一个实例 可用于处理单元的事务操作到独占高速缓存一致性状态。

公开(公告)号：US20150169384A1

公开(公告)日：2015-06-18

申请号：US14635790

申请日：2015-03-02

Applicant: Intel Corporation

Inventor： Suresh Srinivas ,  Stephen H. Dohrmann ,  Mingqiu Sun ,  Uma Srinivasan ,  Ravi Rajwar ,  Konrad K. Lai

IPC: G06F9/52

CPC classification number: G06F9/528 ,  G06F8/458 ,  G06F9/3842 ,  G06F9/45516 ,  G06F9/526 ,  G06F17/30168 ,  G06F17/30362 ,  Y10S707/99938

Abstract: Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes intercepting a processor request to apply the lock on the object, identifying a performance history of the object based on a number of instances of contention, reducing computing resources of the processor by, when the number of instances is below a threshold value, generating a lock bypass for the object to cause speculative execution of target code within the object, and preventing speculative execution by applying the lock on the object when the number of instances is above the threshold value.

Abstract translation: 公开了用于管理对象锁的示例性方法和装置。 所公开的示例性方法包括拦截处理器请求以对对象施加锁定，基于竞争的多个实例来识别对象的性能历史，当实例数低于阈值时，减少处理器的计算资源 产生对象的锁旁路，以引起对象内的目标代码的推测执行，并且当实例数高于阈值时，通过对对象应用锁来防止推测执行。

公开(公告)号：US10073719B2

公开(公告)日：2018-09-11

申请号：US15131099

申请日：2016-04-18

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Peter Lachner ,  Laura A. Knauth ,  Konrad K. Lai

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/52 ,  G06F11/34 ,  G06F11/36 ,  G06F9/38 ,  G06F9/46 ,  G06F9/30 ,  G06F11/14

CPC classification number: G06F9/528 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/3476 ,  G06F11/3636

Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

公开(公告)号：US20170235638A1

公开(公告)日：2017-08-17

申请号：US15586898

申请日：2017-05-04

Applicant: Intel Corporation

Inventor： Laura A. Knauth ,  Ravi Rajwar ,  Peggy J. Irelan ,  Konrad K. Lai ,  Martin G. Dixon

IPC: G06F11/14 ,  G06F13/42 ,  G06F13/16 ,  G06F11/34 ,  G06F9/30 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0862 ,  G06F11/30

CPC classification number: G06F9/3861 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F9/528 ,  G06F11/1407 ,  G06F11/1469 ,  G06F11/3048 ,  G06F11/3051 ,  G06F11/348 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1673 ,  G06F13/4282 ,  G06F15/80 ,  G06F2201/84 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/62 ,  G06F2213/0026

Abstract: An example system for speculative execution event counter checkpointing and restoring may include a plurality of symmetric cores, at least one of the symmetric cores to simultaneously process a plurality of threads and to perform out-of-order instruction processing for the plurality of threads; at least one shared cache circuit to be shared among two or more the of symmetric cores. The system may further include a memory controller to couple the symmetric cores to a system memory and a data communication interface to couple one or more of the cores to input/output devices. The system may further include event counter circuitry comprising: a plurality of event counters including programmable event counters and fixed event counters and one or more configuration registers to store configuration data to specify an event type to be counted by the programmable event counters, wherein at least one of the one or more configuration registers is to store configuration data for a plurality of the programmable event counters. The system may further include transactional memory circuitry to process transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to indicate a start of a transactional execution region of a program, a transaction end instruction to indicate an end of the transactional execution region, and a transaction abort instruction to abort processing of the transactional execution region. The system may further include transaction checkpoint circuitry to store a processor state at the start of the transactional execution region of the program, the processor state including values of one or more of the event counters. The system may further include lock elision circuitry to cause critical sections of the program to execute as transactions on multiple threads without acquiring a lock, the lock elision circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.

公开(公告)号：US20170235579A1

公开(公告)日：2017-08-17

申请号：US15586636

申请日：2017-05-04

Applicant: Intel Corporation

Inventor： Laura A. Knauth ,  Ravi Rajwar ,  Peggy J. Irelan ,  Konrad K. Lai ,  Martin G. Dixon

IPC: G06F9/38 ,  G06F9/46 ,  G06F12/0875 ,  G06F12/084 ,  G06F15/80 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F9/528 ,  G06F11/1407 ,  G06F11/1469 ,  G06F11/3048 ,  G06F11/3051 ,  G06F11/348 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1673 ,  G06F13/4282 ,  G06F15/80 ,  G06F2201/84 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/62 ,  G06F2213/0026

Abstract: An example processor for speculative execution event counter checkpointing and restoring may include a plurality of symmetric cores, at least one of the symmetric cores to simultaneously process a plurality of threads and to perform out-of-order instruction processing for the plurality of threads; at least one shared cache circuit to be shared among two or more the of symmetric cores. The processor may further include event counter circuitry comprising: a plurality of event counters including programmable event counters and fixed event counters and one or more configuration registers to store configuration data to specify an event type to be counted by the programmable event counters, wherein at least one of the one or more configuration registers is to store configuration data for a plurality of the programmable event counters. The processor may further include transactional memory circuitry to process transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to indicate a start of a transactional execution region of a program, a transaction end instruction to indicate an end of the transactional execution region, and a transaction abort instruction to abort processing of the transactional execution region. The processor may further include transaction checkpoint circuitry to store a processor state at the start of the transactional execution region of the program, the processor state including values of one or more of the event counters. The processor may further include lock elision circuitry to cause critical sections of the program to execute as transactions on multiple threads without acquiring a lock, the lock elision circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.