公开(公告)号：US11669454B2

公开(公告)日：2023-06-06

申请号：US16405691

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Vedaraman Geetha ,  Jeffrey Baxter ,  Sai Prashanth Muralidhara ,  Sharada Venkateswaran ,  Daniel Liu ,  Nishant Singh ,  Bahaa Fahim ,  Samuel D. Strom

IPC: G06F12/0817

CPC classification number: G06F12/0817 ,  G06F2212/1021 ,  G06F2212/608

Abstract: A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.

公开(公告)号：US20210342134A1

公开(公告)日：2021-11-04

申请号：US17033751

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Lihu Rappoport ,  Jared W. Stark ,  Jeffrey Baxter ,  Israel Diamand ,  Pavel Fridman ,  Ibrahim Hur ,  Nir Tell

IPC: G06F8/41

Abstract: Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.