公开(公告)号：US20170256019A1

公开(公告)日：2017-09-07

申请号：US15062691

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Kritika Bala ,  Murali Ramadoss ,  Hema Nalluri ,  Jeffery Boles ,  Jeffrey Frizzell ,  Joseph Koston

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/4881 ,  G06F2009/45579

Abstract: Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.

公开(公告)号：US10410311B2

公开(公告)日：2019-09-10

申请号：US15062691

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Kritika Bala ,  Murali Ramadoss ,  Hema Nalluri ,  Jeffery Boles ,  Jeffrey Frizzell ,  Joseph Koston

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/48

Abstract: Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.