公开(公告)号：US20030206405A1

公开(公告)日：2003-11-06

申请号：US10447162

申请日：2003-05-27

Applicant: Intel Corporation

Inventor： Longqiang L. Zu ,  Jennifer A. Hester

IPC: H05K001/11 ,  H05K001/14

CPC classification number: H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/0224 ,  H05K1/141 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/049 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10325 ,  H05K2201/10734

Abstract: A circuit package has been described for routing long traces between an electronic circuit, such as a phase locked loop, and external circuit components. The traces are routed through two substrates. In each substrate, the traces are routed primarily on a layer adjacent to and between a pair ground planes located close to the traces. Degassing apertures are located to the side of the long traces to avoid interfering with the shielding provided by the grounds planes. The circuit package uses two power plated through holes and two ground plated through holes to reduce the noise on the power supply lines. The circuit package also separates the signal carrying plated through holes from the power plated through holes, which reduces noise on the long traces. Noise is further reduced on the long traces by using the ground plated through holes to shield the signal carrying plated through holes from noise generated at the power plated through holes.

Abstract translation: 已经描述了用于在电子电路（例如锁相环）和外部电路部件之间路由长走线的电路封装。 迹线穿过两个基板。 在每个基板中，迹线主要在邻近于并且位于靠近迹线的一对接地平面之间的层上。 脱气孔位于长轨迹的侧面，以避免与接地平面所提供的屏蔽干扰。 电路封装使用两个电镀通孔和两个接地电镀通孔，以减少电源线上的噪声。 电路封装还将承载电镀通孔的信号与电源通孔分开，从而降低长走线上的噪音。 通过使用接地电镀通孔来屏蔽穿过电镀通孔的信号，从而在电源通孔上产生的噪声，进一步减小了长走线上的噪音。