公开(公告)号：US20240206055A1

公开(公告)日：2024-06-20

申请号：US18594754

申请日：2024-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonghun SEO

IPC: H05K1/02 ,  H01R12/79 ,  H05K1/14 ,  H05K1/18 ,  H05K5/00

CPC classification number: H05K1/0281 ,  H01R12/79 ,  H05K1/148 ,  H05K1/189 ,  H05K5/0017 ,  H05K2201/093 ,  H05K2201/10151 ,  H05K2201/10189 ,  H05K2201/2009

Abstract: An electronic device is provided. The electronic device includes a flexible printed circuit board comprising a housing, a first printed circuit board disposed in an inner space of the housing, a second printed circuit board disposed so as to be spaced apart from the first printed circuit board, a connection part electrically connecting the first printed circuit board and the second printed circuit board and connected to the second printed circuit board, and a coupling part including a bent part extending from the connection part and capable of being at least partially bent.

公开(公告)号：US20230422409A1

公开(公告)日：2023-12-28

申请号：US18209551

申请日：2023-06-14

Applicant: DONGWOO FINE-CHEM CO., LTD.

Inventor： Dae Kyu KIM ,  Byung Soo BANG ,  Gi Taek OH

IPC: H05K3/46 ,  H05K1/02 ,  H01Q1/22

CPC classification number: H05K3/4605 ,  H05K1/0242 ,  H05K2201/10098 ,  H05K2201/093 ,  H05K2201/10128 ,  H01Q1/2291

Abstract: A circuit board for an antenna may include a core layer, a signal wiring disposed on a surface of the core layer, and a co-planar ground disposed around the signal wiring on the surface of the core layer. The co-planar ground may include line patterns adjacent to a front end portion of the signal wiring.

公开(公告)号：US11812544B2

公开(公告)日：2023-11-07

申请号：US17557877

申请日：2021-12-21

Applicant: XILINX, INC.

Inventor： Shad Shepston ,  Robert Andrew Daniels

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0228 ,  H05K1/0219 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09709 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Apparatus having at least one breakout structure are provided. In one example, an apparatus includes a dielectric layer, first and second contact pads, and first and second vias. The first and second contact pads are disposed on the dielectric layer. The first via is disposed through the dielectric layer and coupled to the first contact pad. The first via is offset from the first contact pad in a first direction. The second contact pad is immediately adjacent the first via. The second via is disposed through the dielectric layer immediately adjacent the first contact pad and coupled to the second contact pad. The second via is offset from the second contact pad in a second direction that is opposite of the first direction. The first and the second contact pads define a first differential pair of contact pads that is configured to transmit a first differential pair of signals.

公开(公告)号：US11729900B2

公开(公告)日：2023-08-15

申请号：US17694201

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Stephen Harvey Hall ,  Khang Choong Yong ,  Ying Ern Ho ,  Yun Rou Lim ,  Wil Choon Song

IPC: H05K1/02 ,  G05B19/4097 ,  H05K3/02 ,  H05K1/18

CPC classification number: H05K1/0225 ,  G05B19/4097 ,  H05K3/027 ,  G05B2219/45026 ,  G05B2219/45034 ,  H05K1/18 ,  H05K2201/093 ,  H05K2201/098 ,  H05K2201/09027 ,  H05K2201/10098

Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.

公开(公告)号：US11710995B2

公开(公告)日：2023-07-25

申请号：US16934872

申请日：2020-07-21

Applicant: Infinitum Electric, Inc.

Inventor： Rich Lee ,  Randal A. Lee ,  Paulo Guedes-Pinto

IPC: H02K3/26 ,  H02K9/22 ,  H05K1/16 ,  H02K1/12 ,  H02K21/24 ,  H02K11/26 ,  H02K11/30 ,  H01F17/00 ,  H01F27/22 ,  H01F27/28 ,  H02K1/18 ,  H05K1/02 ,  H05K1/11

CPC classification number: H02K3/26 ,  H01F17/0013 ,  H01F27/22 ,  H01F27/2804 ,  H02K1/12 ,  H02K1/182 ,  H02K9/22 ,  H02K11/26 ,  H02K11/30 ,  H02K21/24 ,  H05K1/0201 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/165 ,  H01F2017/002 ,  H01F2017/0053 ,  H01F2027/2809 ,  H02K2203/03 ,  H02K2211/03 ,  H05K2201/093 ,  H05K2201/095 ,  H05K2201/10416

Abstract: An axial field rotary energy device has a PCB stator panel assembly between rotors with an axis of rotation. Each rotor has a magnet. The PCB stator panel assembly includes PCB panels. Each PCB panel can have layers, and each layer can have conductive coils. The PCB stator panel assembly can have a thermally conductive layer that extends from an inner diameter portion to an outer diameter portion thereof. Each PCB panel comprises discrete, PCB radial segments that are mechanically and electrically coupled together to form the respective PCB panels.

公开(公告)号：US20190223287A1

公开(公告)日：2019-07-18

申请号：US16244566

申请日：2019-01-10

Applicant: Mitsubishi Electric Corporation

Inventor： Mitsunori NISHIDA ,  Michihiro TAKATA ,  Tomonori KURIYAMA ,  Keita TAKAHASHI

IPC: H05K1/02 ,  H05K1/11 ,  H05K5/00 ,  H05K1/18 ,  B60R16/06

CPC classification number: H05K1/0259 ,  B60R16/06 ,  H05K1/0215 ,  H05K1/0231 ,  H05K1/116 ,  H05K1/181 ,  H05K5/0052 ,  H05K5/006 ,  H05K5/0069 ,  H05K5/0073 ,  H05K5/061 ,  H05K2201/093 ,  H05K2201/09609 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10507

Abstract: A fourth layer outer frame protection pattern of a multilayer circuit board housed in a conductive base and a nonconductive cover is in contact with an inner surface of the base via a selection layer, and is connected to a second layer planar ground pattern via a coupling capacitor, outer peripheral portions of respective layer patterns including a first and third layer annular ground patterns are overlapped with each other, and the planar ground pattern is wire connected to a reference ground point of a vehicle body. When the base is conductively attached to the vehicle body, a selection layer is a solder resist film, and when it is non-conductively attached, the selection layer is a solder film, so that the planar ground pattern does not conduct with the base at the time of short circuit abnormality of the coupling capacitor.

公开(公告)号：US20180310410A1

公开(公告)日：2018-10-25

申请号：US15767376

申请日：2016-10-21

Applicant: AutoNetworks Technologies, Ltd. ,  Sumitomo Wiring Systems, Ltd. ,  SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Arinobu Nakamura ,  Tou Chin

IPC: H05K1/18 ,  H05K7/20 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L23/367 ,  H01L24/00 ,  H05K1/02 ,  H05K1/116 ,  H05K1/18 ,  H05K7/20509 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/10166 ,  H05K2201/10303 ,  H05K2201/10553 ,  H05K2201/10818

Abstract: Provided is a circuit assembly in which the mounting area of a substrate can be increased. A circuit assembly includes an electronic component having a plurality of terminals, a conductive member for supporting the electronic component (10), at least one of the terminals of the electronic component being electrically connected to the conductive member, and a substrate provided with a conductive pattern to which another terminal of the electronic component is electrically connected, in which the substrate is fixed to a surface of the conductive member that is opposite to a surface of the conductive member that supports the electronic component.

公开(公告)号：US20180263109A1

公开(公告)日：2018-09-13

申请号：US15920413

申请日：2018-03-13

Applicant: FOXCONN INTERCONNECT TECHNOLOGY LIMITED

Inventor： CHIN-YU CHEN ,  CHENG-WEN CHEN ,  SHUN-JUNG CHUANG ,  KE-HAO CHEN

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0225 ,  H01R12/707 ,  H01R12/716 ,  H01R12/78 ,  H01R13/20 ,  H05K1/0221 ,  H05K1/0222 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/14 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/09709 ,  H05K2201/09727 ,  H05K2201/10189

Abstract: A multi-layer circuit member includes: a first layer formed of a conductive material, the first layer including plural signal pads and a first reference plane spaced apart from the signal pads, the first reference plane including an outer region surrounding the signal pads and an inner region separating the plurality of signal pads; a second layer formed of a conductive material, the second layer including plural signal conductors and a second reference plane spaced apart from the signal conductors, the second reference plane including an outer region surrounding the signal conductors and an inner region separating the signal conductors; a ground layer disposed at a side of the second layer opposite from the first layer; plural dielectric layers separating the first layer, the second layer, and the ground layer.

公开(公告)号：US20180206335A1

公开(公告)日：2018-07-19

申请号：US15923070

申请日：2018-03-16

Applicant: GigaLane Co., Ltd.

Inventor： Sang Pil KIM ,  Da Yeon Lee ,  Hwang Sub Koo ,  Hyun Je Kim ,  Hee Seok Jung

IPC: H05K1/02 ,  H05K3/28 ,  H05K3/40 ,  H05K3/00 ,  H05K3/06 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0281 ,  H05K1/0219 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0038 ,  H05K3/0044 ,  H05K3/06 ,  H05K3/28 ,  H05K3/4038 ,  H05K3/4644 ,  H05K2201/093 ,  H05K2201/09845 ,  H05K2203/0228 ,  H05K2203/107

Abstract: Provided are a flexible circuit board having enhanced bending durability and a method for preparing same. A method for preparing a flexible circuit board having enhanced bending durability, according to the present invention, comprises the steps of: (a) forming a signal line and a first ground layer on a first dielectric body and forming a second ground layer on the bottom side of the first dielectric body; (b) preparing a second dielectric body; (c) preparing a first bonding sheet and a first protective sheet which is connected to one end of the first boding sheet or of which one or more parts are overlapped on one end of the first bonding sheet; (d) bonding the second dielectric body onto the first dielectric body by means of the first bonding sheet; (e) forming a via hole such that the first ground layer and second ground layer can be conducted; and (f) cutting in the width direction the second dielectric body placed on the first protective sheet.

公开(公告)号：US10020028B2

公开(公告)日：2018-07-10

申请号：US15351600

申请日：2016-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G06F17/50 ,  G11C5/04 ,  G11C5/06 ,  H05K1/18 ,  G11C5/02 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.