公开(公告)号：US20220276958A1

公开(公告)日：2022-09-01

申请号：US17747950

申请日：2022-05-18

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  George VERGIS ,  Tonia M. ROSE ,  John R. GOLES ,  John V. LOVELACE

IPC: G06F12/06

Abstract: A memory chip is described. The memory chip includes self identification circuitry to self identify the memory chip. The self identification circuitry is to determine a resistance of a resistor and correlate the memory chip's identity to the resistance. A registering clock driver (RCD) chip is described. The RCD chip includes a controller. The controller is to receive provisional IDs (PIDs) from memory chips on a same memory module as the RCD chip. The controller is to program the memory chips with respective logical IDs (LIDs) based on a correlation of the PIDs and the LIDs.

公开(公告)号：US20210326041A1

公开(公告)日：2021-10-21

申请号：US17359423

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Arvind KUMAR ,  Dean-Dexter R. EUGENIO ,  John R. GOLES ,  Santhosh MUSKULA

IPC: G06F3/06 ,  G06N20/00

Abstract: In a memory system, reference voltage training per path provides the capability to train receiver and transmitter reference voltages to optimal values based on selected feedback per path from the memory device. Training receiver reference voltages to an optimal receiver reference voltage per path includes programming dedicated mode registers that enable a local receiver voltage reference adjuster circuit to adjust the receiver reference voltage per path to the optimal receiver reference voltage per path. Transmitter reference voltage training includes the capability to also train an optimal input timing delay for an optimal transmitter reference voltage. Reference voltage training can be performed by a host component and/or a test system having access to the selected feedback per path of the memory device undergoing training.

公开(公告)号：US20200159429A1

公开(公告)日：2020-05-21

申请号：US16702359

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Dean-Dexter R. EUGENIO ,  Arvind KUMAR ,  John R. GOLES ,  Christopher E. COX

IPC: G06F3/06 ,  G06F11/22 ,  G06F13/16

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

公开(公告)号：US20210327524A1

公开(公告)日：2021-10-21

申请号：US17359442

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Arvind KUMAR ,  Dean-Dexter R. EUGENIO ,  John R. GOLES

IPC: G11C29/10 ,  G06N20/00 ,  G11C29/12

Abstract: In a memory system, receiver reference voltage adjustment per path provides the capability to adjust receiver reference voltages on a per path basis. Adjustment of receiver reference voltages for the memory device to an optimal receiver reference voltage per path is accomplished with dedicated mode registers and a local receiver voltage reference adjuster circuit in the memory device for each data path. The optimal receiver reference voltage is determined during training based on selected feedback per path from the memory device. The dedicated mode registers contain adjustment values that were previously programmed during training, and include adjustments steps to add to or subtract from a global receiver reference voltage for all paths until reaching the optimal receiver reference voltage for a current path.

公开(公告)号：US20210247919A1

公开(公告)日：2021-08-12

申请号：US17221728

申请日：2021-04-02

Applicant: Intel Corporation

Inventor： Dean-Dexter R. EUGENIO ,  Arvind KUMAR ,  John R. GOLES ,  Christopher E. COX

IPC: G06F3/06 ,  G06F11/22 ,  G06F13/16

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

公开(公告)号：US20190213148A1

公开(公告)日：2019-07-11

申请号：US16208224

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX ,  Kuljit S. BAINS ,  George VERGIS ,  James A. McCALL ,  Chong J. ZHAO ,  Suneeta SAH ,  Pete D. VOGT ,  John R. GOLES

IPC: G06F13/16 ,  G06F13/40 ,  G11C14/00 ,  G11C11/4096

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4096 ,  G11C14/0009 ,  Y02D10/14 ,  Y02D10/151

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US20200233821A1

公开(公告)日：2020-07-23

申请号：US16827205

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Arvind KUMAR ,  Dean-Dexter R. EUGENIO ,  John R. GOLES

IPC: G06F13/20 ,  G06F13/16

Abstract: An N-bit bus includes (N−1) bidirectional interfaces to couple to (N−1) bidirectional signal lines to exchange (transmit and receive) signals between companion devices. The bus includes two unidirectional signal line interfaces. The first is a unidirectional receive interface to couple to a unidirectional signal line to receive signals from the companion device. The second is a unidirectional transmit interface to couple to a unidirectional signal line to transmit signals to the companion device. The bus provides N signal lines for the N-bit bus in each direction, with an additional “backwards facing” signal line. The backwards facing signal line can allow the devices to prepare for a switch in the direction of the N-bit bus.

公开(公告)号：US20200065266A1

公开(公告)日：2020-02-27

申请号：US16529700

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  John V. LOVELACE ,  John R. GOLES

IPC: G06F13/16 ,  G06F1/10

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

公开(公告)号：US20190095361A1

公开(公告)日：2019-03-28

申请号：US15718346

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  John V. LOVELACE ,  John R. GOLES

IPC: G06F13/16 ,  G06F1/10

CPC classification number: G06F13/1663 ,  G06F1/10 ,  G06F13/1689

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

公开(公告)号：US20180136866A1

公开(公告)日：2018-05-17

申请号：US15811497

申请日：2017-11-13

Applicant: Intel Corporation

Inventor： Dean-Dexter R. EUGENIO ,  Arvind KUMAR ,  John R. GOLES ,  Christopher E. COX

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0635 ,  G06F3/0679 ,  G06F11/22 ,  G06F13/1673 ,  G06F13/1689

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.