公开(公告)号：US20240071913A1

公开(公告)日：2024-02-29

申请号：US17894380

申请日：2022-08-24

Applicant: Intel Corporation

Inventor： June Choi ,  Richard Schenker ,  Charles H. Wallace ,  Nikhil J. Mehta ,  Clifford L. Ong

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329

Abstract: An integrated circuit structure includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes a first interconnect feature and a second interconnect feature. The second interconnect layer includes a third interconnect feature, a fourth interconnect feature, and a fifth interconnection feature. The third interconnect feature extends from an upper surface of the first interconnect feature to an upper surface of the second interconnect layer. In an example, the fourth interconnect feature extends from an upper surface of the second interconnect feature to below the upper surface of the second interconnect layer, and the fifth interconnect feature extends from an upper surface of the fourth interconnect feature to the upper surface of the second interconnect layer. Thus, a double-decked vertical stack of interconnect features is formed using the fourth interconnect feature within the second interconnect layer.

公开(公告)号：US20240170394A1

公开(公告)日：2024-05-23

申请号：US17992818

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Elijah Karpov ,  June Choi ,  Manish Chandhok ,  Miriam Reshotko ,  Matthew Metz

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53257

Abstract: Integrated circuitry comprising an interconnect level with multi-height lines contacted by complementary multi-height vias. In some examples, a first line of a taller height is contacted by a first via of a shorter height while a second line of a shorter height is contacted by a second via of a taller height. The first and second vias and first and second lines may be subtractively defined concurrently from a same stack of conductive material layers such that the first via comprises a first conductive material layer, and the first line comprises second and third conductive material layers while the second via comprises the first and second conductive material layers and the second line comprises the third conductive material layer.

公开(公告)号：US20240145383A1

公开(公告)日：2024-05-02

申请号：US17974945

申请日：2022-10-27

Applicant: Intel Corporation

Inventor： June Choi ,  Keith E. Zawadzki ,  Kimberly L. Pierce ,  Mohammad Enamul Kabir

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/53209

Abstract: An integrated circuit structure includes a device layer including a first set of devices and a second set of devices. An interconnect layer is above the device layer, where the interconnect layer includes one or more conductive interconnect features within dielectric material. In an example, a first ring structure including conductive material extends within the interconnect layer, and a second ring structure including conductive material extends within the interconnect layer. In an example, the second ring structure is non-overlapping with the first ring structure. In an example, the first ring structure is above the first set of devices of the device layer, and the second ring structure is above the second set of devices of the device layer.

公开(公告)号：US20240105589A1

公开(公告)日：2024-03-28

申请号：US17936014

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Shao Ming Koh ,  Patrick Morrow ,  June Choi ,  Sukru Yemenicioglu ,  Nikhil Jasvant Mehta

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/528

Abstract: An IC device includes a metal layer that includes staggered metal lines. The metal lines are in two or more levels along a direction. There may be one or more metal lines in each level. At least some of the metal lines are aligned along the direction so that widths of the metal lines may be maximized for a given total width of the metal layer. The alignment of the metal lines may be achieved through DSA of a diblock copolymer. The metal layer may be connected to vias in two or more levels. The vias may be also connected to another metal layer or a semiconductor device in a FEOL section of the IC device. A via and the metal line connected to the via may be formed through a same recess and deposition process to eliminate interface between the via and metal line.

公开(公告)号：US20240096785A1

公开(公告)日：2024-03-21

申请号：US17933000

申请日：2022-09-16

Applicant: Intel Corporation

Inventor： June Choi ,  Charles Henry Wallace ,  Richard E. Schenker ,  Nikhil Jasvant Mehta

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242

Abstract: An IC device includes a transistor, a first layer, and a second layer. The first layer is coupled to the transistors and is between the transistor and the second layer in a first direction. The first layer includes a first structure and a second structure. The first structure includes a first metal (e.g., Ru). The second structure includes a second metal (e.g., Cu). The second structure may be wrapped around by a different material that may include a third metal (e.g., Co). The first structure may be shorter than the second structure in the first direction and narrower than the second structure in a second direction orthogonal to the first direction. The first structure may be closer to the second layer than the second structure in the first direction. The first structure may be a wordline of a memory. The second structure may be a bitline.