公开(公告)号：US11652060B2

公开(公告)日：2023-05-16

申请号：US16236228

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Rajabali Koduri ,  Leonard Neiberg ,  Altug Koker ,  Swaminathan Sivakumar

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L21/78 ,  H01L21/66 ,  H01L23/528 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01L21/78 ,  H01L22/20 ,  H01L23/528 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/94 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/73209

Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.