公开(公告)号：US20230369192A1

公开(公告)日：2023-11-16

申请号：US18226652

申请日：2023-07-26

Applicant: Intel Corporation

Inventor： Jonathan ROSCH ,  Wei-Lun JEN ,  Cheng XU ,  Liwei CHENG ,  Andrew BROWN ,  Yikang DENG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49827 ,  H05K1/111 ,  H01L21/486 ,  H05K1/115 ,  H01L23/49822 ,  H05K2201/09727 ,  H05K1/025 ,  H05K2201/09736 ,  H05K2201/09827 ,  H05K1/18 ,  H05K2201/095

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US20240332195A1

公开(公告)日：2024-10-03

申请号：US18129879

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Naiya SOETAN-DODD ,  Srinivas V. PIETAMBARAM ,  Suddhasattwa NAD ,  Brandon C. MARIN ,  Sheng C. LI ,  Liwei CHENG

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16235

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a core, where the core comprises glass. In an embodiment, a cavity is in the core, and a bridge is in the cavity. In an embodiment, the bridge comprises through substrate vias (TSVs). In an embodiment, pads are at a bottom of the cavity, where the TSVs are electrically coupled to the pads.

公开(公告)号：US20190393143A1

公开(公告)日：2019-12-26

申请号：US16017671

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Jonathan ROSCH ,  Wei-Lun JEN ,  Cheng XU ,  Liwei CHENG ,  Andrew BROWN ,  Yikang DENG

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.