公开(公告)号：US20210405090A1

公开(公告)日：2021-12-30

申请号：US16912612

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Liwei Zhao ,  Andrew Martwick ,  Michael W. Altmann ,  Michael Mirmak ,  Kamel Ahmad ,  Andrew Holland

IPC: G01R13/02

Abstract: A scheme for noise floor de-embedding by identifying a link or relationship between noise floor from an oscilloscope and phase jitter impact on a toggling signal. The scheme uses phase or electrical spectrum and phase detection for noise floor recognition. The scheme de-embeds the impact from random noise and also removes deterministic noise or jitter from the oscilloscope. The scheme provides accurate jitter analysis for a circuit (e.g., clock data recovery circuit) after de-embedding noise floor for the oscilloscope

公开(公告)号：US11532906B2

公开(公告)日：2022-12-20

申请号：US17041262

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Yi Huang ,  Fernando Gonzalez Lenero ,  Liwei Zhao

IPC: H05K1/02 ,  H01R13/24 ,  H01R12/70 ,  H01R12/71

Abstract: A power delivery system for a hardware processor includes a motherboard (MB), a voltage regulator (VR), an elastomer computer socket, and a plurality of power delivery paths within the socket. The socket connects the MB to the processor and comprises a first set of power pins that is connected to the processor by surface mount elements, and a second set of power pins that is not connected to the processor by surface mount elements. The plurality of electrical power delivery paths deliver VR power from the second set of C power pins to the first set of power pins for power delivery to the processor. The alignment frame aligns the processor, the plurality of power pins, and the MB. The plurality of power paths alone may meet the power demands of the processor. If not, a power plane from the MB provides additional power.

公开(公告)号：US20230402990A1

公开(公告)日：2023-12-14

申请号：US18134850

申请日：2023-04-14

Applicant: Intel Corporation

Inventor： Jason A. Mix ,  Liwei Zhao ,  Alexander T. Hoang ,  Sarah Shahraini ,  Ruth Y. Vidana Morales ,  Andrew Martwick ,  Andrea S. Muljono

IPC: H03H9/02 ,  H03H9/13

CPC classification number: H03H9/02574 ,  H03H9/02031 ,  H03H9/02228 ,  H03H9/132

Abstract: Clock distribution in an integrated circuit component can comprise the generation of bulk acoustic waves by acoustic transmitters and propagation of the bulk acoustic waves across the substrate where they are received by piezoelectric elements acting as acoustic receivers.
Clock distribution can also comprise the generation of surface acoustic waves by acoustic transmitters located on the same substrate surface as the piezoelectric elements.
An acoustic transmitter comprises a layer of piezoelectric material that generates an acoustic wave in response to the piezoelectric layer being activated by a clock source signal applied to the acoustic transmitter. The piezoelectric elements convert the acoustic waves into an electrical signal which can be used as a local clock signal for devices and components in the vicinity of the piezoelectric elements or from which such a local clock signal can be derived.

公开(公告)号：US11614468B2

公开(公告)日：2023-03-28

申请号：US16912612

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Liwei Zhao ,  Andrew Martwick ,  Michael W. Altmann ,  Michael Mirmak ,  Kamel Ahmad ,  Andrew Holland

IPC: G01R13/02

Abstract: A scheme for noise floor de-embedding by identifying a link or relationship between noise floor from an oscilloscope and phase jitter impact on a toggling signal. The scheme uses phase or electrical spectrum and phase detection for noise floor recognition. The scheme de-embeds the impact from random noise and also removes deterministic noise or jitter from the oscilloscope. The scheme provides accurate jitter analysis for a circuit (e.g., clock data recovery circuit) after de-embedding noise floor for the oscilloscope.

公开(公告)号：US20210057840A1

公开(公告)日：2021-02-25

申请号：US17041262

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Yi Huang ,  Fernando Gonzalez Lenero ,  Liwei Zhao

IPC: H01R13/24 ,  H01R12/70 ,  H01R12/71

Abstract: A power delivery system for a hardware processor includes a motherboard (MB), a voltage regulator (VR), an elastomer computer socket, and a plurality of power delivery paths within the socket. The socket connects the MB to the processor and comprises a first set of power pins that is connected to the processor by surface mount elements, and a second set of power pins that is not connected to the processor by surface mount elements. The plurality of electrical power delivery paths deliver VR power from the second set of C power pins to the first set of power pins for power delivery to the processor. The alignment frame aligns the processor, the plurality of power pins, and the MB. The plurality of power paths alone may meet the power demands of the processor. If not, a power plane from the MB provides additional power.