公开(公告)号：US20190034120A1

公开(公告)日：2019-01-31

申请号：US15858067

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Mariusz Barczak ,  Dhruvil Shah ,  Kapil Karkra ,  Andrzej Jakowski ,  Piotr Wysocki

IPC: G06F3/06

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a stream classification for an access request to a persistent storage media, and assign the access request to a stream based on the stream classification. Other embodiments are disclosed and claimed.

公开(公告)号：US12282683B2

公开(公告)日：2025-04-22

申请号：US17430693

申请日：2020-03-12

Applicant: Intel Corporation

Inventor： Michael P. Mesnier ,  John S. Keys ,  Ian F. Adams ,  Yi Zou ,  Luis Carlos Maria Remis ,  Daniel Robert McLeran ,  Mariusz Barczak ,  Arun Raghunath ,  Lay Wai Kong

IPC: G06F3/06

Abstract: In one embodiment, a system comprises a host processor and a storage system. The storage system comprises one or more storage devices, and each storage device comprises a non-volatile memory and a compute offload controller. The non-volatile memory stores data, and the compute offload controller performs compute tasks on the data based on compute offload commands from the host processor.

公开(公告)号：US20190095336A1

公开(公告)日：2019-03-28

申请号：US15718032

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Mariusz Barczak

IPC: G06F12/0868 ,  G06F9/455 ,  G06F3/06 ,  G06F17/30

Abstract: A host computing arrangement is provided, which may include a host processor having a host operating system and host kernel associated therewith. The host processor may be configured to host a guest operating system, mirror a filesystem of the guest operating system via the host kernel, and generate caching criteria by scanning the mirrored filesystem. The host computing arrangement may further include a cache engine. The cache engine may be configured to process an I/O request from the guest operating system based on the caching criteria generated by the host processor.

公开(公告)号：US20180067854A1

公开(公告)日：2018-03-08

申请号：US15258521

申请日：2016-09-07

Applicant: Intel Corporation

Inventor： Maciej Kaminski ,  Mariusz Barczak

IPC: G06F12/0804 ,  G06F12/0842 ,  G06F12/0868 ,  G06F12/0873

CPC classification number: G06F12/0868 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/222

Abstract: Methods and apparatus related to an aggressive write-back cache cleaning policy optimized for Non-Volatile Memory (NVM) are described. In one embodiment, dirty cache lines are sorted by their LBA (Logic Block Address) on backend storage and an attempt is made to first flush (or remove) the largest sequential portions (including one or more cache lines). Other embodiments are also disclosed and claimed.

公开(公告)号：US12204470B2

公开(公告)日：2025-01-21

申请号：US17331101

申请日：2021-05-26

Applicant: Intel Corporation

Inventor： Maksymilian Kunt ,  Piotr Wysocki ,  Mariusz Barczak

IPC: G06F13/24 ,  G06F13/16

Abstract: Dynamically controlled interrupt coalescing is performed by enabling interrupt coalescing when the queue depth of the submission queue is high and disabling interrupt coalescing when the queue depth of the submission queue is low to maintain a required quality of service for a solid state drive. The minimum number of completions in the completion queue to trigger an interrupt is modified based on the queue depth of the submission queue. The minimum number of completions is increased when there is an increase in the queue depth of the submission queue and decreased when there is a decrease in the queue depth of the submission queue.

公开(公告)号：US10318450B2

公开(公告)日：2019-06-11

申请号：US15201056

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Maciej Kaminski ,  Piotr Wysocki ,  Mariusz Barczak

IPC: G06F13/18 ,  G06F13/364 ,  G06F13/16

Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to define a caching and processing priority policy for one or more input/output (I/O) request class types. The memory controller can monitor one or more I/O contexts of one or more I/O requests. The memory controller can associate the one or more I/O contexts with one or more I/O class types using an I/O context association table. The memory controller can execute the one or more I/O requests according to the caching and processing priority policy of the one or more I/O class types. The apparatus can include an interface to the memory controller.

公开(公告)号：US20180188985A1

公开(公告)日：2018-07-05

申请号：US15394059

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Piotr Wysocki ,  Mariusz Barczak

IPC: G06F3/06 ,  G06F12/0802 ,  G06F9/455

CPC classification number: G06F3/0622 ,  G06F3/0659 ,  G06F3/0685 ,  G06F9/45558 ,  G06F12/0802 ,  G06F2009/45579 ,  G06F2212/1052 ,  G06F2212/60

Abstract: An embodiment of a storage apparatus may include persistent storage media, a namespace having backend storage, and a virtual function controller communicatively coupled to the persistent storage media and the namespace to assign the namespace to a virtual storage function and to control access to the namespace by the virtual storage function. The virtual function controller may be further configured to cache access to the namespace on the persistent storage media. Other embodiments are disclosed and claimed.

公开(公告)号：US12093563B2

公开(公告)日：2024-09-17

申请号：US17084301

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Kapil Karkra ,  Mariusz Barczak ,  Michal Wysoczanski ,  Sanjeev Trika ,  James Guilmart

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0688 ,  G06F2212/7201

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to manage access to a storage system that includes a first persistent storage device and a second persistent storage device, capture input/output telemetry for a workload on the storage system, determine one or more write reduction factors and one or more write invalidation factors for the workload based on the captured input/output telemetry, and allocate storage for the workload between the first persistent storage device and the second persistent storage device based on the one or more write reduction factors and the one or more write invalidation factors. Other embodiments are disclosed and claimed.

公开(公告)号：US20220188028A1

公开(公告)日：2022-06-16

申请号：US17430693

申请日：2020-03-12

Applicant: Intel Corporation

Inventor： Michael P. Mesnier ,  John S. Keys ,  Ian F. Adams ,  Yi Zou ,  Luis Carlos Maria Remis ,  Daniel Robert McLeran ,  Mariusz Barczak ,  Arun Raghunath ,  Lay Wai Kong

IPC: G06F3/06

Abstract: In one embodiment, a system comprises a host processor and a storage system. The storage system comprises one or more storage devices, and each storage device comprises a non-volatile memory and a compute offload controller. The non-volatile memory stores data, and the compute offload controller performs compute tasks on the data based on compute offload commands from the host processor.

公开(公告)号：US20220107733A1

公开(公告)日：2022-04-07

申请号：US17551755

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Sanjeev Trika ,  Kapil Karkra ,  Mariusz Barczak

IPC: G06F3/06 ,  G06F11/30

Abstract: An embodiment of an electronic apparatus may comprise a processor, memory communicatively coupled to the processor, and circuitry communicatively coupled to the processor and the memory to determine a group of available types of persistent memory devices and a set of characteristics associated with each type of persistent memory device of the group of available types of persistent memory devices, determine of a set of requirements for a storage system, and determine a deployment configuration for the storage system with a lowest storage acquisition cost based on the group of available types of persistent memory devices, the sets of characteristics, and the set of requirements. Other embodiments are disclosed and claimed.