公开(公告)号：US11688792B2

公开(公告)日：2023-06-27

申请号：US17526986

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/762 ,  H01L21/76895 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US11205708B2

公开(公告)日：2021-12-21

申请号：US15943556

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US11605632B2

公开(公告)日：2023-03-14

申请号：US17529029

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon ,  Sairam Subramanian

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/528

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US11217582B2

公开(公告)日：2022-01-04

申请号：US15941647

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon ,  Sairam Subramanian

IPC: H01L27/088 ,  H01L29/66 ,  H01L23/528 ,  H01L29/06 ,  H01L21/8234

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US09076814B2

公开(公告)日：2015-07-07

申请号：US14297847

申请日：2014-06-06

Applicant: Intel Corporation

Inventor： Cory Weber ,  Mark Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

IPC: H01L29/76 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

Abstract translation: 提供了一种设备。 该器件包括形成在半导体衬底上的晶体管，该晶体管具有导通沟道。 该器件包括与半导体衬底上的导电沟道相邻形成的至少一个边缘位错。 该装置还包括在导电通道之上引入的至少一个自由表面和至少一个边缘错位。

公开(公告)号：US11329138B2

公开(公告)日：2022-05-10

申请号：US15943552

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Christopher Kenyon ,  Sridhar Govindaraju ,  Chia-Hong Jan ,  Mark Liu ,  Szuya S. Liao ,  Walid M. Hafez

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.