公开(公告)号：US20220206819A1

公开(公告)日：2022-06-30

申请号：US17134335

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Gilles Pokam ,  Asit Mallick ,  Martin Dixon ,  Michael Chynoweth

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability mitigation hardware and speculation vulnerability detection hardware. The speculation vulnerability mitigation hardware is to implement one or more of a plurality of speculation vulnerability mitigation mechanisms. The speculation vulnerability detection hardware to detect vulnerability to a speculative execution attack and to provide to software an indication of speculative execution attack vulnerability.

公开(公告)号：US20220114136A1

公开(公告)日：2022-04-14

申请号：US17558172

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Ivan Chen ,  Barnes Cooper ,  Jianwei Dai ,  Martin Dixon ,  Kristoffer Fleming ,  Mark Gallina ,  Duncan Glendinning ,  Deepak Samuel Kirubakaran ,  Chia-Hung S. Kuo ,  Yifan Li ,  Adam Norman ,  Michael Rosenzweig ,  Kai P Wang ,  Jin Yan ,  Virendra Vikramsinh Adsure

IPC: G06F15/78 ,  G06F9/445

Abstract: Methods, systems, and apparatus to reconfigure a computer are disclosed. An example electronic device includes at least one memory, instructions in the electronic device, and processor circuitry to execute instructions to analyze data corresponding to a first configuration of the electronic device to detect a change associated with the electronic device, the first configuration corresponding to a respective first user profile, determine a second configuration of the electronic device based on the detected change, and adjust a configuration of the electronic device from the first configuration to the second configuration.

公开(公告)号：US20220207154A1

公开(公告)日：2022-06-30

申请号：US17134333

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Richard Winterton ,  Mohammad Reza Haghighat ,  Asit Mallick ,  Alaa Alameldeen ,  Abhishek Basak ,  Jason W. Brandt ,  Michael Chynoweth ,  Carlos Rozas ,  Scott Constable ,  Martin Dixon ,  Matthew Fernandez ,  Fangfei Liu ,  Francis McKeen ,  Joseph Nuzman ,  Gilles Pokam ,  Thomas Unterluggauer ,  Xiang Zou

IPC: G06F21/60 ,  H04L9/08 ,  H04L9/30

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.

公开(公告)号：US09417880B2

公开(公告)日：2016-08-16

申请号：US13843558

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Martin Dixon ,  Baiju Patel ,  Rajeev Gopalakrishna

IPC: G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30076 ,  G06F9/3802 ,  G06F9/3838 ,  G06F9/3861

Abstract: A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether substantive data from a larger source data size will fit within a smaller data size that the substantive data is to flow to.

Abstract translation: 描述了处理器在指令执行流水线内具有功能单元。 功能单元具有用于确定来自较大源数据大小的实质数据是否适合实质数据要流向的较小数据大小的电路。

公开(公告)号：US09325498B2

公开(公告)日：2016-04-26

申请号：US13790748

申请日：2013-03-08

Applicant: Intel Corporation

Inventor： Martin Dixon ,  Srinivas Chennupaty ,  Shay Gueron

IPC: G06F21/00 ,  H04L9/28 ,  H04L9/06

CPC classification number: H04L9/0631 ,  G06F9/30007 ,  H04L9/0637 ,  H04L9/28 ,  H04L2209/12

Abstract: A machine-readable medium may have stored thereon an instruction, which when executed by a machine causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction.

公开(公告)号：US20220197829A1

公开(公告)日：2022-06-23

申请号：US17128804

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Martin Dixon ,  Abhishek Sharma

IPC: G06F12/14 ,  G06F12/06 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/0882

Abstract: An embodiment of an apparatus may include a processor, memory communicatively coupled to the processor, and circuitry communicatively coupled to the processor and the memory, the circuitry to manage a portion of the memory as hidden memory outside a range of physical memory accessible by user applications, and control access to the hidden memory from the processor with hidden page tables. Other embodiments are disclosed and claimed.

公开(公告)号：US20160261406A1

公开(公告)日：2016-09-08

申请号：US15079305

申请日：2016-03-24

Applicant: Intel Corporation

Inventor： Martin Dixon ,  Srinivas Chennupaty ,  Shay Gueron

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  G06F9/30007 ,  H04L9/0637 ,  H04L2209/12

Abstract: A machine-readable medium may have stored thereon an instruction, which when executed by a machine causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction.

公开(公告)号：US08913740B2

公开(公告)日：2014-12-16

申请号：US13791224

申请日：2013-03-08

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Martin Dixon ,  Srinivas Chennupaty ,  Mayank Bomb ,  Brent Boswell

IPC: H04K1/00 ,  H04L9/00 ,  H04L9/28 ,  H04L9/06

CPC classification number: H04L9/28 ,  G06F9/30007 ,  H04L9/0631 ,  H04L2209/125 ,  H04L2209/24

Abstract: An Advanced Encryption Standard (AES) key generation assist instruction is provided. The AES key generation assist instruction assists in generating round keys used to perform AES encryption and decryption operations. The AES key generation instruction operates independent of the size of the cipher key and performs key generation operations in parallel on four 32-bit words thereby increasing the speed at which the round keys are generated. This instruction is easy to use in software. Hardware implementation of this instruction removes potential threats of software (cache access based) side channel attacks on this part of the AES algorithm.

Abstract translation: 提供了高级加密标准（AES）密钥生成辅助指令。 AES密钥生成辅助指令有助于生成用于执行AES加密和解密操作的循环密钥。 AES密钥生成指令独立于密码密钥的大小，并行执行四个32位字的密钥生成操作，从而增加生成循环密钥的速度。 该指令在软件中易于使用。 该指令的硬件实现可以消除这部分AES算法对软件（基于缓存访问的）侧面信道攻击的潜在威胁。