公开(公告)号：US20180101482A1

公开(公告)日：2018-04-12

申请号：US15784625

申请日：2017-10-16

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Martin P. Dimitrov ,  Thomas Willhalm

IPC: G06F12/1027 ,  G06F12/0862

CPC classification number: G06F12/1027 ,  G06F9/00 ,  G06F12/0862 ,  G06F13/16 ,  G06F2212/1024 ,  G06F2212/221

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

公开(公告)号：US20170116133A1

公开(公告)日：2017-04-27

申请号：US14921809

申请日：2015-10-23

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Martin P. Dimitrov ,  Thomas Willhalm

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/00 ,  G06F12/0862 ,  G06F13/16 ,  G06F2212/1024 ,  G06F2212/221

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

公开(公告)号：US10346091B2

公开(公告)日：2019-07-09

申请号：US15324107

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Thomas Willhalm ,  Karthik Kumar ,  Martin P. Dimitrov ,  Raj K. Ramanujan

IPC: G06F3/06 ,  G06F12/0815

Abstract: Methods and apparatus related to fabric resiliency support for atomic writes of many store operations to remote nodes are described. In one embodiment, non-volatile memory stores data corresponding to a plurality of write operations. A first node includes logic to perform one or more operations (in response to the plurality of write operations) to cause storage of the data at a second node atomically. The plurality of write operations are atomically bound to a transaction and the data is written to the non-volatile memory in response to release of the transaction. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180329650A1

公开(公告)日：2018-11-15

申请号：US15324107

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Thomas Willhalm ,  Karthik Kumar ,  Martin P. Dimitrov ,  Raj K. Ramanujan

IPC: G06F3/06 ,  G06F12/0815

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0656 ,  G06F3/067 ,  G06F3/0688 ,  G06F12/0815 ,  G06F2212/621 ,  Y02D10/154

Abstract: Methods and apparatus related to fabric resiliency support for atomic writes of many store operations to remote nodes are described. In one embodiment, non-volatile memory stores data corresponding to a plurality of write operations. A first node includes logic to perform one or more operations (in response to the plurality of write operations) to cause storage of the data at a second node atomically. The plurality of write operations are atomically bound to a transaction and the data is written to the non-volatile memory in response to release of the transaction. Other embodiments are also disclosed and claimed.

公开(公告)号：US09792224B2

公开(公告)日：2017-10-17

申请号：US14921809

申请日：2015-10-23

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Martin P. Dimitrov ,  Thomas Willhalm

IPC: G06F12/08 ,  G06F12/1027 ,  G06F12/0862

CPC classification number: G06F12/1027 ,  G06F9/00 ,  G06F12/0862 ,  G06F13/16 ,  G06F2212/1024 ,  G06F2212/221

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

公开(公告)号：US20170123796A1

公开(公告)日：2017-05-04

申请号：US14926336

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Martin P. Dimitrov

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30047 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0888 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/20 ,  G06F2212/214 ,  G06F2212/452 ,  G06F2212/6028

Abstract: In one embodiment, a processor includes a core having a fetch logic to fetch instructions, a decode logic to decode a first persistent memory prefetch instruction and provide the decoded first persistent memory prefetch instruction to a control logic. In turn, the control logic is to enable prefetch of data requested by the first persistent memory prefetch instruction and storage of the data in a location external to the processor. Other embodiments are described and claimed.

公开(公告)号：US10977036B2

公开(公告)日：2021-04-13

申请号：US16336884

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Patrick Lu ,  Karthik Kumar ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Martin P. Dimitrov

IPC: G06F12/08 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/0862 ,  G06F9/38

Abstract: An apparatus is described. The apparatus includes main memory control logic circuitry comprising prefetch intelligence logic circuitry. The prefetch intelligence circuitry to determine, from a read result of a load instruction, an address for a dependent load that is dependent on the read result and direct a read request for the dependent load to a main memory to fetch the dependent load's data.

公开(公告)号：US10169245B2

公开(公告)日：2019-01-01

申请号：US15784625

申请日：2017-10-16

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Martin P. Dimitrov ,  Thomas Willhalm

IPC: G06F12/08 ,  G06F12/1027 ,  G06F12/0862 ,  G06F13/16 ,  G06F9/00

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.