公开(公告)号：US20230420528A1

公开(公告)日：2023-12-28

申请号：US17851658

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Nitesh Kumar ,  Willy Rachmady ,  Cheng-Ying Huang ,  Rohit Galatage ,  Patrick Morrow ,  Marko Radosavljevic ,  Jami A. Wiedemer ,  Subrina Rafique ,  Mauro J. Kobrinsky

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L29/41733 ,  H01L29/0847 ,  H01L29/401 ,  H01L27/088 ,  H01L29/0673

Abstract: An integrated circuit structure includes a source or drain region, and a contact for the source or drain region. The contact has (i) an upper portion outside the source or drain region and (ii) a lower portion extending within the source or drain region. For example, the source or drain region wraps around the lower portion of the contact, such that an entire perimeter of the lower portion of the contact is adjacent to the source or drain region.

公开(公告)号：US20230187509A1

公开(公告)日：2023-06-15

申请号：US17550861

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Urusa Alaan ,  Scott B. Clendenning ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Nitesh Kumar

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

Abstract: Techniques are provided herein to form semiconductor devices having an epi region contact with a high contact area to either or both top and bottom epi regions in a stacked transistor configuration. In one example, two different semiconductor devices include an n-channel device located vertically above a p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device, such that a source or drain region of one device is located vertically over the source or drain region of the other device. A contact structure may be formed that has a greater width when contacting a top surface of the bottom source or drain region than when contacting a side surface of the top source or drain region. The higher contact area on the bottom source or drain region provides a lower contact resistance compared to previous architectures.

公开(公告)号：US20230395717A1

公开(公告)日：2023-12-07

申请号：US17833045

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Nitesh Kumar ,  Jami A. Wiedemer ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Patrick Morrow ,  Rohit Galatage ,  David N. Goldstein ,  Christopher J. Jezewski

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/45 ,  H01L27/092

CPC classification number: H01L29/7845 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/45 ,  H01L27/092

Abstract: An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

公开(公告)号：US20230395718A1

公开(公告)日：2023-12-07

申请号：US17833050

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Nitesh Kumar ,  Jami A. Wiedemer ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Patrick Morrow ,  Rohit Galatage ,  David N. Goldstein ,  Christopher J. Jezewski

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/7845 ,  H01L29/42392 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/45

Abstract: An integrated circuit structure includes a vertical stack including a first device, and a second device above the first device. The first device includes (i) a first source and first drain region, (ii) a first body laterally between the first source and drain regions, (iii) a first source contact including a first conductive material, and (iv) a first drain contact including the first conductive material. The second device includes (i) a second source and second drain region, (ii) a second body laterally between the second source and drain regions, (iii) a second source contact including a second conductive material, and (iv) a second drain contact including the second conductive material. In an example, the first and second conductive materials are compositionally different. In an example, the first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

公开(公告)号：US20240053973A1

公开(公告)日：2024-02-15

申请号：US17972378

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Vidya Ranganathan ,  Aditya Shukla ,  Nitesh Kumar ,  Jitendra Kumar Saini

IPC: G06F8/61 ,  G06F9/445 ,  G06F21/57

CPC classification number: G06F8/63 ,  G06F9/44505 ,  G06F21/577

Abstract: Various systems and methods are described for deployment, import, and scheduling of containers and other software components on cloud and edge computing hardware. A development platform may receive, from a remote location, package data for a deployment of one or more containers, including a configuration for the one or more containers. Such package data may be provided by a Helm chart or a Docker Compose YAML file. The development platform may extract the configuration for the one or more containers from the package data, and also perform a security evaluation of the one or more containers and the configuration for the one or more containers to validate compliance with a security policy. The development platform may execute (and coordinate scheduling) of one or more container images for the one or more containers, based on the configuration, after validating compliance with the security policy.

公开(公告)号：US20230402513A1

公开(公告)日：2023-12-14

申请号：US17838646

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Rohit Galatage ,  Willy Rachmady ,  Subrina Rafique ,  Nitesh Kumar ,  Cheng-Ying Huang ,  Jami A. Wiedemer ,  Nicloe K. Thomas ,  Munzarin F. Qayyum ,  Patrick Morrow ,  Marko Radosavljevic ,  Mauro J. Kobrinsky

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66742 ,  H01L29/66439

Abstract: An integrated circuit structure includes a device including a source region, a drain region, a body laterally between the source and drain regions, and a source contact coupled to the source region. In an example, the source region includes a first region, and a second region compositionally different from and above the first region. The source contact extends through the second region and extends within the first region. In an example where the device is a p-channel metal-oxide-semiconductor (PMOS) device, a concentration of germanium within the second region is different (e.g., higher) than a concentration of germanium within the first region. In another example where the device is a n-channel metal-oxide-semiconductor (NMOS) device, a doping concentration level of a dopant (e.g., an n-type dopant) within the second region is different (e.g., higher) from a doping concentration level of the dopant within the first region.

公开(公告)号：US20230395678A1

公开(公告)日：2023-12-07

申请号：US17831802

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Munzarin F. Qayyum ,  Nicole K. Thomas ,  Jami A. Wiedemer ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Willy Rachmady ,  Cheng-Ying Huang ,  Rohit Galatage ,  Nitesh Kumar ,  Kai Loon Cheong ,  Venkata Vasiraju

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L27/092

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/41733 ,  H01L27/0924

Abstract: A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.

公开(公告)号：US11594637B2

公开(公告)日：2023-02-28

申请号：US16833208

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Stephen Snyder ,  Biswajeet Guha ,  William Hsu ,  Urusa Alaan ,  Tahir Ghani ,  Michael K. Harper ,  Vivek Thirtha ,  Shu Zhou ,  Nitesh Kumar

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L21/02 ,  H01L29/10

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

公开(公告)号：US20230197818A1

公开(公告)日：2023-06-22

申请号：US17559342

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Nitesh Kumar ,  William Hsu ,  Mohammad Hasan ,  Ritesh Das ,  Vivek Thirtha ,  Biswajeet Guha ,  Oleg Golonzka

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L21/823418

Abstract: Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately for NMOS and PMOS gate-all-around transistors by implementing selective masking techniques. The resulting transistor structures have improved cavity spacer integrity and contact to gate isolation.

公开(公告)号：US11569370B2

公开(公告)日：2023-01-31

申请号：US16454408

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Vivek Thirtha ,  Shu Zhou ,  Nitesh Kumar ,  Biswajeet Guha ,  William Hsu ,  Dax Crum ,  Oleg Golonzka ,  Tahir Ghani ,  Christopher Kenyon

IPC: H01L29/66 ,  H01L21/31 ,  H01L29/06 ,  H01L21/3105

Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.