公开(公告)号：US20220285288A1

公开(公告)日：2022-09-08

申请号：US17192770

申请日：2021-03-04

Applicant: Intel Corporation

Inventor： Valery Ouvarov-Bancalero ,  John Harper ,  Malavarayan Sankarasubramanian ,  Patrick Nardi ,  Bamidele Daniel Falola ,  Ravi Siddappa ,  James Mertens

IPC: H01L23/00 ,  H01L23/06 ,  H05K7/14

Abstract: A stiffener for an integrated circuit (IC) package assembly including an IC die electrically interconnected to a substrate. The stiffener is to be mechanically attached to the substrate adjacent to at least one edge of the IC die and have a coefficient of linear thermal expansion (CTE) exceeding that of the substrate. The stiffener may be an “anti-invar” metallic alloy. Anti-invar alloys display “anti-invar” behavior where thermal expansion of the material is significantly enhanced relative to other compositions of the particular alloy system. A package stiffener may be a high-Mn steel, for example, such as ASTM International A128. In other examples, a package stiffener is a MnCuNi, FeNiMn, or FeNiCr alloy having an average CTE over a range of 25-100° C. of at least 18 ppm, and a room temperature modulus of elasticity of at least 120 GPa.

公开(公告)号：US20160005672A1

公开(公告)日：2016-01-07

申请号：US14323077

申请日：2014-07-03

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Patrick Nardi ,  David Woodhams

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L23/24 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die.

Abstract translation: 一些实施例涉及电子包装。 电子封装包括基板和附接到基板的裸片。 电子封装还包括由于毛细管作用而位于管芯和衬底之间的底部填充物。 支架围绕着模具。 支撑件在所有模具边缘上提供相同的有益的圆角几何形状。 因此，支撑件在所有模具边缘上提供类似的应力减小。 其他实施例涉及制造电子封装的方法。 该方法包括将管芯附接到衬底并且使用毛细管作用将底部填充物插入管芯和衬底之间。 该方法还包括将支撑件放置在模具周围，使得支撑件围绕模具。

公开(公告)号：US09230877B2

公开(公告)日：2016-01-05

申请号：US13724511

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Patrick Nardi ,  Kelly P. Lofgreen

IPC: H01L21/00 ,  H01L23/34 ,  H01L23/367 ,  G06F1/20 ,  F28F3/02

CPC classification number: H01L23/3672 ,  F28F3/025 ,  G06F1/20 ,  H01L23/49568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/0002 ,  H01L2924/16152 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal interface material comprising a thermally conductive serpentine foil located between a first and a second interface material. The serpentine foil may be in a parallel position or a rotated position, in embodiments.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 那些方法可以包括形成热界面材料，该热界面材料包括位于第一和第二界面材料之间的导热蛇形箔。 在实施例中，蛇形箔可以处于平行位置或旋转位置。

公开(公告)号：US10535615B2

公开(公告)日：2020-01-14

申请号：US15548741

申请日：2016-02-12

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Srikant Nekkanty ,  Rajendra C. Dias ,  Patrick Nardi

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/498 ,  H01L23/58

Abstract: An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a different material.

公开(公告)号：US20180033741A1

公开(公告)日：2018-02-01

申请号：US15548741

申请日：2016-02-12

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Srikant Nekkanty ,  Rajendra C. Dias ,  Patrick Nardi

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/585 ,  H01L2924/3511

Abstract: An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a different material.

公开(公告)号：US20170186667A1

公开(公告)日：2017-06-29

申请号：US14757997

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Arnab Choudhury ,  Patrick Nardi ,  William Nicholas Labanok ,  Kelly P. Lofgreen

IPC: H01L23/473 ,  H01L23/00 ,  H01L21/48 ,  H01L23/053 ,  G06F1/20 ,  H01L23/367

CPC classification number: H01L23/473 ,  G06F1/20 ,  G06F2200/201 ,  H01L21/4878 ,  H01L21/4882 ,  H01L23/053 ,  H01L23/3672 ,  H01L24/32 ,  H01L2224/32245

Abstract: Embodiments are generally directed to cooling of electronics using folded foil microchannels. An embodiment of an apparatus includes a semiconductor die; a substrate, the semiconductor die being coupled with the substrate; and a cooling apparatus for the semiconductor die, wherein the cooling apparatus includes a folded foil preform, the folded foil forming a plurality of microchannels, and a fluid coolant system to direct a fluid coolant through the microchannels of the folded foil.

公开(公告)号：US12183688B2

公开(公告)日：2024-12-31

申请号：US17192770

申请日：2021-03-04

Applicant: Intel Corporation

Inventor： Valery Ouvarov-Bancalero ,  John Harper ,  Malavarayan Sankarasubramanian ,  Patrick Nardi ,  Bamidele Daniel Falola ,  Ravi Siddappa ,  James Mertens

IPC: H01L23/00 ,  H01L23/06 ,  H05K7/14

Abstract: A stiffener for an integrated circuit (IC) package assembly including an IC die electrically interconnected to a substrate. The stiffener is to be mechanically attached to the substrate adjacent to at least one edge of the IC die and have a coefficient of linear thermal expansion (CTE) exceeding that of the substrate. The stiffener may be an “anti-invar” metallic alloy. Anti-invar alloys display “anti-invar” behavior where thermal expansion of the material is significantly enhanced relative to other compositions of the particular alloy system. A package stiffener may be a high-Mn steel, for example, such as ASTM International A128. In other examples, a package stiffener is a MnCuNi, FeNiMn, or FeNiCr alloy having an average CTE over a range of 25-100° C. of at least 18 ppm, and a room temperature modulus of elasticity of at least 120 GPa.

公开(公告)号：US09887104B2

公开(公告)日：2018-02-06

申请号：US14323077

申请日：2014-07-03

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Patrick Nardi ,  David Woodhams

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/24 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/24 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die.

公开(公告)号：US09832860B2

公开(公告)日：2017-11-28

申请号：US14498958

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Robert Starkston ,  John Guzek ,  Patrick Nardi ,  Keith Jones ,  Javier Soto Gonzalez

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/16 ,  H01L23/498 ,  H05K3/00 ,  H05K3/28

CPC classification number: H05K1/0271 ,  H01L23/16 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/284 ,  H05K2201/09136 ,  H05K2201/10977 ,  H05K2201/2009

Abstract: Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.

公开(公告)号：US10651108B2

公开(公告)日：2020-05-12

申请号：US15197440

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Zhizhong Tang ,  Syadwad Jain ,  Wei Hu ,  Michael A. Schroeder ,  Rajen S. Sidhu ,  Carl L. Deppisch ,  Patrick Nardi ,  Kelly P. Lofgreen ,  Manish Dubey

IPC: H05K5/00 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01L23/42 ,  F28F13/00 ,  F28F21/04 ,  F28F21/02 ,  F28F21/08 ,  F28D21/00

Abstract: Devices and methods disclosed herein can include a conductive foam having pores disposed within the conductive foam. The conductive foam can be compressible between an uncompressed thickness and a compressed thickness. The compressed thickness can be ninety-five percent or less of the uncompressed thickness. In one example, a filler can be disposed in the pores of the conductive foam. The filler can include a first thermal conductivity. The first thermal conductivity can be greater than a thermal conductivity of air.