公开(公告)号：US20230100829A1

公开(公告)日：2023-03-30

申请号：US18070361

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Sheue Fen Yong ,  Archanna Srinivasan ,  Graham Baker ,  Pheak Ti Teh

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

Abstract: An integrated circuit package includes a first integrated circuit die, a spacer die coupled in the integrated circuit package in a location designed to house a second integrated circuit die, and a package substrate coupled to the first integrated circuit die and to the spacer die.

公开(公告)号：US20210183758A1

公开(公告)日：2021-06-17

申请号：US17030080

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Mohd Muhaiyiddin Bin Abdullah ,  Lee Ping Loh ,  Pheak Ti Teh ,  Ken Beng Lim

IPC: H01L23/498 ,  H01L23/64 ,  H01L21/48

Abstract: Disclosed embodiments include conductive polygon power and ground interconnects in an infield formed by an electrical contact array. The conductive polygon ground interconnects are orthogonally reticulated an among the conductive polygon power interconnects, for integrated-circuit device packages that provide a low-loss path to active and passive devices, by minimizing resistive loops.