Board to board interconnect
    1.
    发明授权

    公开(公告)号:US11304299B2

    公开(公告)日:2022-04-12

    申请号:US17008222

    申请日:2020-08-31

    Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

    Board to board interconnect
    2.
    发明授权

    公开(公告)号:US10356902B2

    公开(公告)日:2019-07-16

    申请号:US14757984

    申请日:2015-12-26

    Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

    DEVICE, SYSTEM AND METHOD TO MITIGATE LOSS OF SIGNAL INTEGRITY IN A COMMUNICATION OF IMAGE INFORMATION

    公开(公告)号:US20170289410A1

    公开(公告)日:2017-10-05

    申请号:US15085926

    申请日:2016-03-30

    CPC classification number: H04N5/213 G06T5/20 H01P1/20

    Abstract: Techniques and mechanisms for exchanging image data via a three-wire data channel of an interconnect, at least a portion of which is disposed in or on a substrate of a printed circuit board. In an embodiment, three data signals are concurrently exchanged in parallel, each via a different respective trace portion of the data channel. The substrate has disposed therein or thereon three filter structures each to perform filtering of a different respective one of the three signals. The filter structures each include a respective sequence of corrugations to increase a stray capacitance provided by a substrate material. In another embodiment, the interconnect is compatible with a Mobile Industry Processor Interface (MIPI) camera physical layer interface (C-PHY) standard.

    Board to board interconnect
    5.
    发明授权

    公开(公告)号:US10772206B2

    公开(公告)日:2020-09-08

    申请号:US16513004

    申请日:2019-07-16

    Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

    BOARD TO BOARD INTERCONNECT
    6.
    发明申请

    公开(公告)号:US20190342996A1

    公开(公告)日:2019-11-07

    申请号:US16513004

    申请日:2019-07-16

    Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

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