公开(公告)号：US20240105860A1

公开(公告)日：2024-03-28

申请号：US17955235

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Tahir Ghani ,  WIlfred Gomes ,  Anand Murthy ,  Sagar Suthram ,  Pushkar Ranade

IPC: H01L29/93 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/93 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66174

Abstract: An integrated circuit (IC) die includes a plurality of varactor devices, where at least one varactor of the plurality of varactor devices comprises a first electrode, a second electrode, and a multi-layer stack of ferroelectric material (e.g., ferroelectric variable capacitance material) disposed between the first and second electrodes. Other embodiments are disclosed and claimed.

公开(公告)号：US20230317140A1

公开(公告)日：2023-10-05

申请号：US17708448

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Rajabali Koduri ,  Pushkar Ranade ,  Wilfred Gomes

IPC: G11C11/408 ,  G11C11/4094 ,  H03K19/17728 ,  H03K19/0185

CPC classification number: G11C11/4087 ,  G11C11/4094 ,  G11C11/4085 ,  H03K19/17728 ,  H03K19/018521

Abstract: In one embodiment, a memory comprises: a first subarray having a first plurality of memory cells, the first subarray having a first orientation; and a second subarray having a second plurality of memory cells, the second subarray having a second orientation, the second orientation orthogonal to the first orientation. Other embodiments are described and claimed.

公开(公告)号：US20240105700A1

公开(公告)日：2024-03-28

申请号：US17955253

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Tahir Ghani ,  Anand Murthy ,  Wilfred Gomes ,  Sagar Suthram ,  Pushkar Ranade

IPC: H01L25/18 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5286 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1431

Abstract: An embodiment of an integrated circuit (IC) device may include a plurality of layers of wide bandgap (WBG)-based circuitry and a plurality of layers of silicon (Si)-based circuitry monolithically bonded to the plurality of layers of WBG-based circuitry, with one or more electrical connections between respective WBG-based circuits in the plurality of layers of WBG-based circuitry and Si-based circuits in the plurality of layers of Si-based circuitry. In some embodiments, a wafer-scale WBG-based IC is hybrid bonded or layer transfer bonded to a wafer-scale Si-based IC. Other embodiments are disclosed and claimed.

公开(公告)号：US20240105635A1

公开(公告)日：2024-03-28

申请号：US17955187

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand Murthy ,  Sagar Suthram ,  Pushkar Ranade

IPC: H01L23/544 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3205 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L23/544 ,  H01L21/0226 ,  H01L21/306 ,  H01L21/3205 ,  H01L23/481 ,  H01L23/5329

Abstract: An integrated circuit (IC) die includes a first layer with conductive structures formed in a interlayer dielectric (ILD) material, with a portion of the conductive structures at a first surface of the first layer, a self-alignment layer in contact with non-conductive regions at the first surface of the first layer, a second layer with ILD material in contact with the self-alignment layer and the portion of the conductive structures at the first surface of the first layer, and conductive vias through the self-alignment layer and the second layer in contact with the portion of the conductive structures at the first surface of the first layer. The self-alignment layer may include a first material where the self-alignment layer is in contact with the conductive vias and a second material where the self-alignment layer is not in contact with the conductive vias. Other embodiments are disclosed and claimed.

公开(公告)号：US20240105248A1

公开(公告)日：2024-03-28

申请号：US17955194

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Tahir Ghani ,  Sagar Suthram ,  Anand Murthy ,  Wilfred Gomes ,  Pushkar Ranade

IPC: G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/66 ,  H01L29/78

CPC classification number: G11C11/2275 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

Abstract: An integrated circuit (IC) die includes a substrate and an array of memory cells formed in or on the substrate with a memory cell of the array of memory cells that includes a storage circuit that comprises a hysteretic-oxide material. A ternary content-addressable memory (TCAM) may utilize hysteretic-oxide memory cells. Other embodiments are disclosed and claimed.

公开(公告)号：US20230418604A1

公开(公告)日：2023-12-28

申请号：US17850044

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Pushkar Ranade ,  Wilfred Gomes ,  Sagar Suthram

IPC: G06F9/30 ,  G06F9/445 ,  G06F9/50

CPC classification number: G06F9/30036 ,  G06F9/5016 ,  G06F9/44505

Abstract: In one embodiment, a memory includes a die having: one or more memory layers having a plurality of banks to store data; and at least one other layer comprising at least one reconfigurable vector processor, the at least one reconfigurable vector processor to perform a vector computation on input vector data obtained from at least one bank of the plurality of banks and provide processed vector data to the at least one bank. Other embodiments are described and claimed.

公开(公告)号：US20230318825A1

公开(公告)日：2023-10-05

申请号：US17708431

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Pushkar Ranade ,  Wilfred Gomes

IPC: H04L9/08 ,  G06F21/72

CPC classification number: H04L9/0894 ,  G06F21/72 ,  H04L9/0819

Abstract: In one embodiment, an apparatus includes: at least one core to execute operations on data; a cryptographic circuit to perform cryptographic operations; a static random access memory (SRAM) coupled to the at least one core; and a ferroelectric memory coupled to the at least one core. In response to a read request, the SRAM is to provide an encryption key to the cryptographic circuit and the ferroelectric memory is to provide encrypted data to the cryptographic circuit, the encryption key associated with the encrypted data. Other embodiments are described and claimed.

公开(公告)号：US20230317794A1

公开(公告)日：2023-10-05

申请号：US17712057

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Sagar Suthram ,  Pushkar Ranade ,  Rajabali Koduri

IPC: H01L29/10 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L23/427

CPC classification number: H01L29/1037 ,  H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/7851 ,  H01L29/66795 ,  H01L23/427 ,  H01L29/247

Abstract: Narrow-channel, non-planar transistors and their manufacture on integrated circuit dies. A method includes forming channel portions of transistors from sidewall spacers by removing backbone features and coupling a gate structure, a source, and a drain to the channel portions. An integrated circuit die includes a gate structure, a source, and a drain coupled to pair-symmetric channel portions with sidewalls of differing heights. A method includes iteratively etching away portions of semiconductor material not covered by a mask or a passivation layer, revealing a channel portion by removing the mask and passivation layer, and coupling a gate structure, a source, and a drain to the channel portion. An integrated circuit die includes a gate structure, a source, and a drain coupled to a channel portion with vertically alternating, greater and lesser widths.

公开(公告)号：US09847420B2

公开(公告)日：2017-12-19

申请号：US15473503

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Pushkar Ranade

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/417 ,  H01L29/08 ,  H01L29/51 ,  H01L29/267 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/0228 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/28167 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/31055 ,  H01L21/31604 ,  H01L21/47 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78654

Abstract: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

公开(公告)号：US20170207336A1

公开(公告)日：2017-07-20

申请号：US15473503

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Pushkar Ranade

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/417 ,  H01L29/08 ,  H01L21/28 ,  H01L29/267 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L21/0228 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/28167 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/31055 ,  H01L21/31604 ,  H01L21/47 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78654

Abstract: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.