公开(公告)号：US20200185226A1

公开(公告)日：2020-06-11

申请号：US16334324

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Rahim KASIM ,  Manish CHANDHOK ,  Florian Gstrein

IPC: H01L21/302 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.

公开(公告)号：US20240421101A1

公开(公告)日：2024-12-19

申请号：US18211084

申请日：2023-06-16

Applicant: Intel Corporation

Inventor： Sunny CHUGH ,  Rahim KASIM ,  Mohammad Enamul KABIR ,  Jasmeet S. CHAWLA ,  Mauro J. KOBRINSKY ,  Joseph D’SILVA

IPC: H01L23/00 ,  H01L23/50 ,  H01L23/58

Abstract: Guard rings are described. In an example, a semiconductor die includes an active device layer including a plurality of nanoribbon devices. A dielectric structure is over the active device layer. A first die-edge metal guard ring is in the dielectric structure and around an outer perimeter of the plurality of nanoribbon devices. A plurality of metallization layers is in the dielectric structure and within the first die-edge metal guard ring. A plurality of direct backside contacts extend to the active device layer. A plurality of backside metallization structures is beneath the plurality of direct backside contacts. The plurality of direct backside contacts are connected to the plurality of backside metallization structures. A second die-edge metal guard ring is laterally around the plurality of backside metallization structures.

公开(公告)号：US20240363490A1

公开(公告)日：2024-10-31

申请号：US18140146

申请日：2023-04-27

Applicant: Intel Corporation

Inventor： Mohammad Enamul KABIR ,  Keith ZAWADZKI ,  Rahim KASIM ,  Sunny CHUGH ,  Zhizheng ZHANG ,  Christopher M. PELTO ,  Babita DHAYAL ,  John Kevin TAYLOR ,  Doug INGERLY

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/58 ,  H01L29/06

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/585 ,  H01L24/16 ,  H01L29/0619 ,  H01L2224/16225

Abstract: Through-silicon via dies are described. In an example, a semiconductor die includes a substrate having a device side and a backside. An active device layer is in or on the device side of the substrate. A dielectric structure is over the active device layer. A first die-edge metal guard ring is in the dielectric structure and around an outer perimeter of the substrate. A plurality of metallization layers is in the dielectric structure and within the first die-edge metal guard ring. A plurality of through silicon vias is in the substrate and extend into the dielectric structure and are connected to the plurality of metallization layers. A plurality of backside metallization structures is beneath the backside of the substrate. The plurality of through silicon vias are connected to the plurality of backside metallization structures. A second die-edge metal guard ring is laterally around the plurality of backside metallization structures.