公开(公告)号：US09870640B2

公开(公告)日：2018-01-16

申请号：US14961755

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Rahul P. Sathe ,  Tim Foley

IPC: G09G5/36 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T2200/28

Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.

公开(公告)号：US09626795B2

公开(公告)日：2017-04-18

申请号：US14108419

申请日：2013-12-17

Applicant: Intel Corporation

Inventor： Rahul P. Sathe

IPC: G06T15/50 ,  G06T15/80 ,  G06T17/20

CPC classification number: G06T17/20 ,  G06T15/005 ,  G06T15/80

Abstract: Instead of shading a triangle from the rasterizer as soon as it is known that there is a sample inside the triangle, in accordance with one embodiment, shading is delayed until the triangle beside it, called the neighboring triangle, is received. If there is a neighboring triangle facing the same way, with non-mutually exclusive coverage, meaning that it is not overlapping the same region, then the shader shades only once for the pair of triangles. That is, two separate fragments are merged and treated as one fragment. Specifically, the fragment that is over the pixel center is the one that is used and the other fragment is replaced by merging. The merger happens only over the extent of a pixel and more than one primitive is not shaded at a time. However, multiple merges within a 2×2 block of pixels are possible.

公开(公告)号：US10262455B2

公开(公告)日：2019-04-16

申请号：US14959185

申请日：2015-12-04

Applicant: Intel Corporation

Inventor： Gabor Liktor ,  Marco Salvi ,  Rahul P. Sathe

IPC: G09G5/36 ,  G06T11/40 ,  G06T15/00 ,  G06T15/50 ,  G06T15/80 ,  G06T17/20

Abstract: Two primitives may be merged by interpolating vertex attributes at coarse pixel centers. Input attributes are computed as a coverage weighted average of the interpolated vertex attributes. Then coarse pixel shading is performed using the merged primitives.

公开(公告)号：US09934606B2

公开(公告)日：2018-04-03

申请号：US14487432

申请日：2014-09-16

Applicant: Intel Corporation

Inventor： Rahul P. Sathe ,  Marco Salvi

IPC: G06T15/80 ,  G06T15/00 ,  G09G5/36

CPC classification number: G06T15/80 ,  G06T15/005 ,  G09G5/363 ,  G09G2350/00 ,  G09G2360/08 ,  G09G2360/121

Abstract: A shading rate may be set by analyzing samples within a pixel. Then based on that analysis, a system determines whether to use coarse pixel, pixel or sample shading for a region of pixels. Based on the determined type of shading, the shading rate may be set.

公开(公告)号：US10403024B2

公开(公告)日：2019-09-03

申请号：US15988157

申请日：2018-05-24

Applicant: Intel Corporation

Inventor： Bimal Poddar ,  Prasoonkumar Surti ,  Rahul P. Sathe

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/04 ,  G06T15/50 ,  G06T19/20

Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

公开(公告)号：US10140678B2

公开(公告)日：2018-11-27

申请号：US15089270

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Saurabh Sharma ,  Abhishek Ventakesh ,  Travis T. Schluessler ,  Thomas F. Raoux ,  Rahul P. Sathe ,  Jon Hasselgren

IPC: G06T1/20 ,  G06F8/41 ,  G06F9/38 ,  G06T15/00

Abstract: Techniques to improve graphics processing unit (GPU) performance by introducing specialized code paths to process frequent common values are described. A shader compiler can determine instruction that, during operation, may output a common value and can introduce an enhanced shader instruction branch to process the common value to reduce overall computational requirements to execute the shader.

公开(公告)号：US20180268597A1

公开(公告)日：2018-09-20

申请号：US15988157

申请日：2018-05-24

Applicant: Intel Corporation

Inventor： Bimal Poddar ,  Prasoonkumar Surti ,  Rahul P. Sathe

IPC: G06T15/00 ,  G06T15/50 ,  G06T1/60 ,  G06T15/04 ,  G06T19/20

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T15/04 ,  G06T15/506 ,  G06T19/20 ,  G06T2200/04 ,  G06T2200/28 ,  G06T2210/62

Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

公开(公告)号：US20170372519A1

公开(公告)日：2017-12-28

申请号：US15195005

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Rahul P. Sathe

IPC: G06T19/00 ,  G06T15/00 ,  G06T1/60 ,  G06T15/80 ,  G06T1/20

CPC classification number: G06T1/60

Abstract: One embodiment provides for a graphics processing apparatus comprising first logic to rasterize pixel regions associated with multiple interleaved primitives; second logic to shade pixel regions covered by one or more of the multiple interleaved primitives; and third logic to interleave output of the second logic for the multiple interleaved primitives to a single render target, the single render target including output associated with the multiple interleaved primitives.

公开(公告)号：US20170186227A1

公开(公告)日：2017-06-29

申请号：US15407304

申请日：2017-01-17

Applicant: Intel Corporation

Inventor： Rahul P. Sathe

IPC: G06T17/20 ,  G06T15/00 ,  G06T15/80

CPC classification number: G06T17/20 ,  G06T15/005 ,  G06T15/80

Abstract: Instead of shading a triangle from the rasterizer as soon as it is known that there is a sample inside the triangle, in accordance with one embodiment, shading is delayed until the triangle beside it, called the neighboring triangle, is received. If there is a neighboring triangle facing the same way, with non-mutually exclusive coverage, meaning that it is not overlapping the same region, then the shader shades only once for the pair of triangles. That is, two separate fragments are merged and treated as one fragment. Specifically, the fragment that is over the pixel center is the one that is used and the other fragment is replaced by merging. The merger happens only over the extent of a pixel and more than one primitive is not shaded at a time. However, multiple merges within a 2×2 block of pixels are possible.

公开(公告)号：US20170061569A1

公开(公告)日：2017-03-02

申请号：US14843698

申请日：2015-09-02

Applicant: Intel Corporation

Inventor： Rahul P. Sathe

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: In one embodiment a graphics processing system comprises a graphics processor having execution logic and shared memory and a shader compiler unit to compile a shader program for execution by the execution logic of the graphic processor, wherein the shader is to optimize the shader program during the compile, wherein to optimize the shader program includes to convert a divergent block of parallel instructions into a divergent block and a non-divergent block of instructions.

Abstract translation: 在一个实施例中，图形处理系统包括具有执行逻辑和共享存储器的图形处理器和着色器编译器单元，用于编译着色器程序以供图形处理器的执行逻辑执行，其中着色器将在编译期间优化着色器程序 其中为了优化着色器程序包括将并行指令的发散块转换成发散块和非发散块指令。