公开(公告)号：US20230420574A1

公开(公告)日：2023-12-28

申请号：US17847555

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Ashish Agrawal ,  Jack T. Kavalieros ,  Rambert Nahm ,  Natalie Briggs ,  Susmita Ghose ,  Glenn Glass ,  Devin R. Merrill ,  Aaron A. Budrevich ,  Shruti Subramanian ,  Biswajeet Guha ,  William Hsu ,  Adedapo A. Oni ,  Rahul Ramamurthy ,  Anupama Bowonder ,  Hsin-Ying Tseng ,  Rajat K. Paul ,  Marko Radosavljevic

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392

Abstract: Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.

公开(公告)号：US20240006499A1

公开(公告)日：2024-01-04

申请号：US17854242

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Kai Loon Cheong ,  Pooja Nath ,  Susmita Ghose ,  Rambert Nahm ,  Natalie Briggs ,  Charles C. Kuo ,  Nicole K. Thomas ,  Munzarin F. Qayyum ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Thoe Michaelos ,  David Kohen

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/6681

Abstract: An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.

公开(公告)号：US20230134379A1

公开(公告)日：2023-05-04

申请号：US17517925

申请日：2021-11-03

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Urusa Alaan ,  Susmita Ghose ,  Rambert Nahm ,  Natalie Briggs ,  Nicole K. Thomas ,  Willy Rachmady ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices, such as those having a stacked transistor configuration. In one example case, two different semiconductor devices may both be GAA transistors each having any number of nanoribbons extending in the same (e.g., horizontal) direction where one device is located vertically above the other device. An internal spacer structure extends between the nanoribbons of both devices along the vertical direction, where the spacer structure includes one or more rib features between the two devices. A gate structure that includes one or more gate dielectric layers and one or more gate electrode layers may be formed around the nanoribbons of both devices, in some cases. In other cases, a split-gate configuration is used where upper and lower gate structures are separated by an isolation structure. Forksheet transistors and other GAA configurations may be formed using the techniques as well.