公开(公告)号：US11070200B2

公开(公告)日：2021-07-20

申请号：US16144949

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Aaron Martin ,  Roger Cheng ,  Hari Venkatramani ,  Navneet Dour ,  Mozhgan Mansuri ,  Bryan Casper ,  Frank O'Mahony ,  Ganesh Balamurugan ,  Ajay Balankutty ,  Kuan Zhou ,  Sridhar Tirumalai ,  Krishnamurthy Venkataramana ,  Alex Thomas ,  Quoc Nguyen

IPC: H03K5/156 ,  H03L7/081 ,  G11C7/22 ,  G06F1/08 ,  G11C7/10

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

公开(公告)号：US11722128B2

公开(公告)日：2023-08-08

申请号：US17357456

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Aaron Martin ,  Roger Cheng ,  Hari Venkatramani ,  Navneet Dour ,  Mozhgan Mansuri ,  Bryan Casper ,  Frank O'Mahony ,  Ganesh Balamurugan ,  Ajay Balankutty ,  Kuan Zhou ,  Sridhar Tirumalai ,  Krishnamurthy Venkataramana ,  Alex Thomas ,  Quoc Nguyen

IPC: H03K5/156 ,  H03L7/081 ,  G11C7/22 ,  G06F1/08 ,  G11C7/10

CPC classification number: H03K5/1565 ,  G06F1/08 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0812

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

公开(公告)号：US20240230725A9

公开(公告)日：2024-07-11

申请号：US17972360

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Chia How Low ,  Roger Cheng

IPC: G01R19/10

CPC classification number: G01R19/10

Abstract: Embodiments herein relate to a circuit for evaluating the ground voltage of each circuit partition of a number of circuit partitions, one partition at a time. Once the ground voltage is determined, a corresponding code is stored to control a leakage circuit coupled to the ground node. The leakage circuit provides a leakage current based on the code to offset the ground voltage to a target voltage, which may be common for each of the partitions. The circuit can include a voltage source which supplies a stair step increasing voltage to a comparator. The comparator compares the voltage of the voltage source to the ground node voltage and provides an output which changes when the two input voltages are approximately equal, within a tolerance. The circuit may include a finite state machine for managing the process.

公开(公告)号：US20240133925A1

公开(公告)日：2024-04-25

申请号：US17972360

申请日：2022-10-23

Applicant: Intel Corporation

Inventor： Chia How Low ,  Roger Cheng

IPC: G01R19/10

CPC classification number: G01R19/10

Abstract: Embodiments herein relate to a circuit for evaluating the ground voltage of each circuit partition of a number of circuit partitions, one partition at a time. Once the ground voltage is determined, a corresponding code is stored to control a leakage circuit coupled to the ground node. The leakage circuit provides a leakage current based on the code to offset the ground voltage to a target voltage, which may be common for each of the partitions. The circuit can include a voltage source which supplies a stair step increasing voltage to a comparator. The comparator compares the voltage of the voltage source to the ground node voltage and provides an output which changes when the two input voltages are approximately equal, within a tolerance. The circuit may include a finite state machine for managing the process.

公开(公告)号：US20210320652A1

公开(公告)日：2021-10-14

申请号：US17357456

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Aaron Martin ,  Roger Cheng ,  Hari Venkatramani ,  Navneet Dour ,  Mozhgan Mansuri ,  Bryan Casper ,  Frank O'Mahony ,  Ganesh Balamurugan ,  Ajay Balankutty ,  Kuan Zhou ,  Sridhar Tirumalai ,  Krishnamurthy Venkataramana ,  Alex Thomas ,  Quoc Nguyen

IPC: H03K5/156 ,  H03L7/081 ,  G11C7/22 ,  G06F1/08 ,  G11C7/10

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.